ASN

Archive of 20/22nm

Wafer Leaders Extend Basis for Global SOI Supply Thumbnail

Wafer Leaders Extend Basis for Global SOI Supply

Posted by on October 10, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation. SEH is a $12.7 billion company, supplying over 20% of the […]

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Important News Comes Out of Recent FD-SOI Workshop Thumbnail

Important News Comes Out of Recent FD-SOI Workshop

Posted by on March 9, 2012
In Editor's Blog
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The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product […]

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FD-SOI Workshop in SF Follows ISSCC – Registration (Free!) Now Open Thumbnail

FD-SOI Workshop in SF Follows ISSCC – Registration (Free!) Now Open

Posted on February 7, 2012
In Advanced Substrate Corners, Conferences
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Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator) The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium. It’s a full-day event at […]

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Bulk logic designs for mobile apps port directly to FD-SOI Thumbnail

Bulk logic designs for mobile apps port directly to FD-SOI

Posted by (ARM) on November 4, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of […]

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FDSOI Processes are Cost Competitive with Bulk

Posted by (IC Knowledge LLC) on October 19, 2011
In ASN #18, News & Viewpoints, SOI In Action
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A new study compares processes for the 20/22nm generation at a typical foundry. Silicon On Insulator (SOI) has been in use for state-of-the-art integrated circuit (IC) manufacturing since IBM first championed the technology in the mid-nineties. SOI offers process technologists the option of reducing power or improving performance for a given process node. As process […]

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Major paper on porting SOC designs from bulk to FD-SOI released by SOI Consortium Thumbnail

Major paper on porting SOC designs from bulk to FD-SOI released by SOI Consortium

Posted by on October 3, 2011
In Editor's Blog
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What are you going to do with your SOCs at 20/22nm? The options seem to boil down to just staying on bulk CMOS, or changing to FinFETs or planar, fully-depleted (FD) SOI-based CMOS. Though some may find comfort in staying on bulk CMOS, it’s getting very complicated – and complicated get expensive fast. The FinFET […]

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A comprehensive cost analysis study by research firm IC Knowledge concludes that FD-SOI wafers offer the most cost effective solution compared to bulk silicon for the 22 nm node and beyond

Posted on July 15, 2011
In Industry Buzz
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A comprehensive cost analysis study by research firm IC Knowledge concludes that FD-SOI wafers offer the most cost effective solution compared to bulk silicon for the 22 nm node and beyond. The study uses a Strategic Cost Model to evaluate how process flows would perform in a Taiwanese wafer fab producing 30,000 wafers per month […]

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FD-SOI: A Quick Backgrounder Thumbnail

FD-SOI: A Quick Backgrounder

Posted on May 27, 2011
In ASN #17, Special supplement: SOI Industry Consortium
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For those new to FD-SOI, here’s a short description of the basic principles. FD SOI transistors are constructed on an ultrathin Silicon layer (< 10nm) set on the top of an ultra-thin BOX (thickness <20nm). This architecture represents a fundamental difference from previous generations of SOI and offers a distinct improvement in power, performance and […]

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Bulk to SOI Porting Analysis

Posted on May 27, 2011
In ASN #17, Special supplement: SOI Industry Consortium
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One of the key projects currently underway within the SOI Consortium is to understand and provide guidance on the advantages and obstacles of porting SoC designs from Bulk to FD-SOI. This project represents a strategic opportunity to help drive the profile of FD SOI and participate in the emergence of this important technology. Objective: Analyze […]

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A Perspective on Multi-Gate MOSFETs Thumbnail

A Perspective on Multi-Gate MOSFETs

Posted by (UF Gainesville) on May 11, 2007
In Advanced Substrate Corners, ASN #7, Professor's Perspective
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One of the world’s leading experts, Professor Fossum explains why SOI represents a pragmatic approach to future transistor generations. Based on our recent studies of multi-gate MOSFETs (“MuGFETs”) for CMOS applications, which are mainly modeling- and simulation-based with experimental support from Freescale Semiconductor, we have suggested that nanoscale FinFETs can and should be designed pragmatically, […]

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