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GlobalFoundries FD-SOI Webinar 24 June 2015, 10am PST: Be There! Thumbnail

GlobalFoundries FD-SOI Webinar 24 June 2015, 10am PST: Be There!

Posted by on June 13, 2015
In Design & Manufacturing, Editor's Blog
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It’s happening! GlobalFoundries is having an FD-SOI technical webinar on the 24th of June 2015. Don’t wait – sign up now – click here to get the registration document. Here’s the information we know so far. Title: Extending Moore’s Law with FD-SOI Technology  Agenda: FD-SOI technology overview Power Performance Area (PPA) advantages Transistor control with […]

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FinFET or FD-SOI? Designers have a real choice, say experts Thumbnail

FinFET or FD-SOI? Designers have a real choice, say experts

Posted by on May 14, 2015
In Editor's Blog
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Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly. Is there a place for FinFETs? Of course there is. If it’s a really big digital chip –  no significant analog integration, where leakage not your biggest […]

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Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016 Thumbnail

Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016

Posted by on April 30, 2015
In Design & Manufacturing, SOI In Action
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ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why. Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts […]

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Newest Leti Compact Model for FD-SOI Further Improves Predictability and Accuracy Thumbnail

Newest Leti Compact Model for FD-SOI Further Improves Predictability and Accuracy

Posted on April 21, 2015
In Industry Buzz
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CEA-Leti’s newest version of its advanced compact model for FD-SOI is now available in all major SPICE simulators (get the press release here). The Leti-UTSOI2.1 is the latest version of Leti’s compact model for FD-SOI, which was first released in 2013. (Compact models of transistors and other elementary devices are used to predict the behavior […]

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Tokyo FD-SOI/RF-SOI Workshop (part 2): Sony 1mW FD-SOI GPS steals the show, but great presentations from EDA & design houses, too Thumbnail

Tokyo FD-SOI/RF-SOI Workshop (part 2): Sony 1mW FD-SOI GPS steals the show, but great presentations from EDA & design houses, too

Posted by on February 9, 2015
In Design & Manufacturing, Editor's Blog
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The Sony presentation on a 28nm FD-SOI GPS chip for an IoT app, which cut power by 10x (down to 1mW), has gained enormous traction worldwide.  However, that was just one of a dozen excellent presentations made by industry leaders at the recent FD-SOI/RF-SOI workshop in Tokyo. In part 1 of ASN’s coverage of the […]

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2015 – Turning the Tables for FD-SOI, RF-SOI and More Thumbnail

2015 – Turning the Tables for FD-SOI, RF-SOI and More

Posted by on January 22, 2015
In Editor's Blog
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If current momentum is any indication, 2015 will be the year the tables turn in favor of FD-SOI designs (with a big shout-out to IoT).  The RF-SOI juggernaut will continue cutting an enormous swath through the mobile market.   Attention to the exciting possibilities of monolithic 3D (M3D) technology (like Leti’s “CoolCube”) will continue to grow, […]

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IEEE SOI-3D-Substhreshold (S3S) Conference Issues Call for Papers

Posted on January 9, 2015
In Industry Buzz
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The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) has issued the 2015 Call for Papers. Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco, October 5-8. This industry-wide event will gather together widely known experts, contributed papers and […]

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SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications Thumbnail

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

Posted by and on November 3, 2014
In Conferences
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ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. […]

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Is China Interested in FD-SOI? You bet. Thumbnail

Is China Interested in FD-SOI? You bet.

Posted by on October 28, 2014
In Conferences, Editor's Blog, In & Around Our Industry
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At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. The event was sponsored by the SOI Consortium, the Shanghai Institute of Microsystem and Information Technology / Chinese Academy of Sciences (SIMIT/CAS), and VeriSilicon. By all accounts it was a great success. Speakers included experts […]

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Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct) Thumbnail

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

Posted by on September 17, 2014
In Conferences, R&D/Labnews
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(For best rates, register by September 18th.) The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco. Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S […]

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