ASN

Archive of 10nm

The SOI Papers at VLSI ’14 (Part 2): Thumbnail

The SOI Papers at VLSI ’14 (Part 2):

Posted by on July 17, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.) This […]

Continue ReadingLeave a Comment
The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs Thumbnail

The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

Posted by on July 11, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
Tagged with , , , , , , , , , , , , , , , , ,

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four […]

Continue ReadingLeave a Comment
14nm FD-SOI Presentation by ST Posted on WeSRCH Thumbnail

14nm FD-SOI Presentation by ST Posted on WeSRCH

Posted on June 17, 2014
In Industry Buzz
Tagged with , , , , ,

A ppt presentation by STMicroelectronics entitled Features and Benefits of 14nm UTBB* FD-SOI Technology is now posted on WeSRCH (click here to view it). It is fairly technical, covering process boosters, modules and innovations, mask sequences, performance and scalability.

Continue ReadingView Comments (1)
2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May Thumbnail

2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May

Posted by on May 22, 2014
In Conferences
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , ,

IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference 6-9 October 2014 Westin San Francisco Airport, Millbrae, CA The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).   Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE […]

Continue ReadingLeave a Comment
Interview: Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain Thumbnail

Interview: Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain

Posted by on May 19, 2014
In Design & Manufacturing, News & Viewpoints
Tagged with , , , , , , , , , , , , , ,

Interview with : Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain With FD-SOI entering the mainstream, fabless designers have been asking about the wafer supply chain. ASN spoke about it with Christophe Maleville, Sr. VP of the Microelectronics business unit at Soitec, the world’s leading SOI wafer producer. Christophe Maleville has been Senior Vice […]

Continue ReadingLeave a Comment
Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
Tagged with , , , , , , , , , , , , , ,

By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

Continue ReadingLeave a Comment
Interview: Leti CEO Laurent Malier on FD-SOI and more Thumbnail

Interview: Leti CEO Laurent Malier on FD-SOI and more

Posted on January 23, 2014
In News & Viewpoints, SOI In Action
Tagged with , , , , , , , , , , , , , , , , ,

CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s […]

Continue ReadingView Comments (1)

Leti Sub-20nm FD-SOI Compact Model Update Now Available for all Major SPICE Simulators

Posted on December 19, 2013
In Industry Buzz
Tagged with , , , , ,

CEA-Leti announced that Leti-UTSOI2, the first complete compact model that enlarges the physically described bias range for designers, is available in all major SPICE simulators (press release here). Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that […]

Continue ReadingLeave a Comment
IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers Thumbnail

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

Posted by on December 19, 2013
In Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices. Brief summaries, culled […]

Continue ReadingLeave a Comment
The FD-SOI Papers at IEDM ’13 Thumbnail

The FD-SOI Papers at IEDM ’13

Posted by on December 16, 2013
In Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , ,

FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI […]

Continue ReadingLeave a Comment