The world’s biggest foundry says its 45nm SOI process technology for the newest generation of high performance CPUs is the best in terms of speed, energy and density in chips using standard nitrided oxide for the gate dielectric. In terms of speed, energy and density, at TSMC we believe we have developed the industry’s best …

CEA-LETI reports on FD-SOI technology developed for the 32nm node and beyond. A Fully Depleted SOI CMOS technology has been developed at CEA-LETI for Low Power applications at 32nm nodes and below. For years, fully depleted devices have been considered as electrostatic boosters due the fact that they benefit from smaller short channel effects than …

Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure? The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has been proposed for scaling CMOS technology to sub-45nm nodes. This is because short-channel effects (manifested in increasing off-state leakage with increasing drain bias and with decreasing gate length) are well suppressed in a FD-SOI MOSFET when the …

FD-SOI enables the use of a slightly different transistor structure than PD-SOI. Each has advantages and disadvantages. Here is a quick layman’s guide to the differences. Partially depleted SOI has been successfully leveraged for high-performance microprocessors and most other SOI applications for almost a decade. Although OKI has used FD-SOI commercially for a long time, …

The ITRS calls for ultra-thin body devices to enter manufacturing in just a few years. The stringent SOI substrate requirements are met with high-volume manufacturing technology. SOI technology is developing toward Ultra-Thin Body (UTB) semiconductor layers with fully depleted (FD-SOI) and Multiple Gate FETs (MuGFETs), consistent with the latest version of the ITRS. The current …

Since the beginning of the decade, OKI has led the world in the mass production of low-power FD-SOI LSIs for personal and mobile markets. While the rest of the industry contemplates moving from partially depleted (PD) to fully depleted (FD) SOI, OKI Electric Industry Company is well ahead of the pack. With an early focus …

With scaling, SRAM design rules are far tighter than logic. New device structures may be needed. 6T SRAMs are the backbone of embedded CMOS memory. Today SRAMs occupy over 50% of the total chip area. The SRAM cell sizes have been shrinking by ~50% each node. Such aggressive scaling has pushed SRAM design rules far …

Jean-Pierre Colinge brings together work from top researchers in physics, design and fabrication of advanced devices. Jean-Pierre Colinge has edited a recent addition to Springer’s Integrated Circuits and Systems Series, entitled FinFETs and Other Multi-Gate Transistors. A well-known figure in the SOI world, Colinge brings together chapters contributed by some of the world’s leading experts …

Bernstein and Rohrer’s introduction to SOI device physics and design concepts guides students and engineers through the fundamentals. Springer has issued a paperback edition of SOI Circuit Design Concepts by Kerry Bernstein and Norman J. Rohrer of IBM. Bernstein recalls that when the book was first published and put on sale at ISSCC in 2000, …

Fifteen partners participating in the program recognized for highly successful collaboration on strained SOI. The European research program SilOnIS, which focused on strained SOI (sSOI), has been honored with the Jean-Pierre Noblanc Award for Excellence. The award is given each year in recognition of the most innovative and sustainable project carried out in the Eureka …