ASN

Archive of ASN #5

Photoreflectance: Promising Metrology on sSOI

Posted by (Optical Metrology Innovations) on July 11, 2006
In ASN #5, Design & Manufacturing, In & Around Our Industry

OMI describes a new approach to in-line strained SOI metrology. Strained-SOI (sSOI) requires fast, accurate and non-contact strain metrology. To address new demands in the engineered substrates industry, several techniques compete: Photoreflectance spectroscopy, Raman spectroscopy, x-ray diffraction and optical birefringence. Photoreflectance appears as one of the most promising of these techniques. Biaxial strain in sSOI […]

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Strained Silicon-On-Insulator (sSOI) Becomes an Industrial Reality Thumbnail

Strained Silicon-On-Insulator (sSOI) Becomes an Industrial Reality

Posted by (Soitec) on July 11, 2006
In Advanced Substrate Corners, ASN #5, R&D/Labnews

After several years of rigorous R&D work in close partnership with suppliers and customers alike, Soitec’s sSOI wafers are now ready for industrialization. The benefits of strained silicon as an amplifier of carrier mobility, current drive and, as a result, device performance are well documented in literature and highlighted by Dr. Nguyen of Freescale in […]

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Strained Engineered Substrates: sSOI and Beyond Thumbnail

Strained Engineered Substrates: sSOI and Beyond

Posted by (MIT) on July 11, 2006
In Advanced Substrate Corners, ASN #5, Professor's Perspective

The semiconductor industry has entered an exciting phase in which further performance gains (power, speed) are directly connected to materials engineering and the insertion of new materials into the heart of silicon integrated circuits. The rate at which the industry is incorporating strain engineering into production is a direct result of using strained substrate materials […]

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Enhanced Strained Silicon-On-Insulator CMOS Devices Thumbnail

Enhanced Strained Silicon-On-Insulator CMOS Devices

Posted by (Freescale) on July 11, 2006
In ASN #5, Design & Manufacturing, In & Around Our Industry

Freescale has investigated a selective biaxial-uniaxial strain hybridization method that significantly enhances drive current without adding process complexity. It has become increasingly difficult to scale CMOS transistors, yet still maintain high drive currents and simultaneously reduce supply voltage (Vdd). This is because threshold voltage and gate oxide thickness cannot be scaled at the same rate […]

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AMD & SOI: Winning with Performance/Watt/Dollar Thumbnail

AMD & SOI: Winning with Performance/Watt/Dollar

Posted on July 11, 2006
In ASN #5, End-User Apps, SOI In Action
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Nick Kepler, vice president of logic technology development at AMD talks about the role of SOI in the company’s strategy. Advanced Substrate News: How important is SOI to your strategy? Nick Kepler: SOI is an important part of AMD’s product strategy. We are currently utilizing it for our entire line of 90nm AMD64 products. AMD […]

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Honeywell & SOI: Military, Aerospace and Beyond Thumbnail

Honeywell & SOI: Military, Aerospace and Beyond

Posted on July 11, 2006
In ASN #5, End-User Apps, SOI In Action
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Honeywell has sent SOI by Jupiter and to Mars. Now its SOI rad-hard foundry services are charting new frontiers with the industry’s first 150 nm rad-hard, digital ASIC solutions and more. Honeywell’s path runs parallel to commercial markets. Chips destined for space are increasingly facing the same performance vs. power issues of chips we find […]

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Partners In Design: Standard Tools Simplify Rad-Hard SOI Design Thumbnail

Partners In Design: Standard Tools Simplify Rad-Hard SOI Design

Posted on July 11, 2006
In ASN #5, End-User Apps, SOI In Action
Tagged with , , , ,

Honeywell has worked with the top EDA tool vendors to develop the SOI process design kits (PDKs) needed by both in-house designers and foundry customers. Rick Veres, Honeywell EDA Manager, explains. ASIC Design With Pilot Flow For digital rad-hard ASIC design, we worked with Synopsys to adapt the Pilot Design Environment to our process. The […]

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A New Generation of Structures Thumbnail

A New Generation of Structures

Posted by (Soitec) on July 11, 2006
In ASN #5, Design & Manufacturing, In & Around Our Industry
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Bonding and thinning technologies pave the way to new substrates for MEMS and power ICs, and enable the transfer of finished circuits to new supports. Layer transfer and direct bonding technologies that leverage molecular adhesion and mechanical and chemical thinning open doors to new generations in advanced and engineered substrates. A spin-off of CEA-Léti, TraciT […]

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The Memory of an SOI Champion Lives On Thumbnail

The Memory of an SOI Champion Lives On

Posted on July 11, 2006
In ASN #5, In & Around Our Industry, People
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Soitec pledges to honor the life’s work of co-founder Jean-Michel Lamure with continued success and passion for the industry. This spring, the advanced substrate community lost a great friend and colleague, Jean-Michel Lamure. An unflagging SOI champion and Soitec co-founder, Jean- Michel spent most of his career in the semiconductor industry. As an award-winning researcher […]

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EE Times Ace Awards Again Honor SOI Innovators Thumbnail

EE Times Ace Awards Again Honor SOI Innovators

Posted on July 11, 2006
In ASN #5, In & Around Our Industry, People
Tagged with , , ,

Freescale’s Leo Mathew was chosen for his novel transistor structure. IBM & Microsoft Design Teams win for Xbox 360™ Leo Mathew, a principal solid state engineer at Freescale Semiconductor, was named Innovator of the Year at the EE Times Annual Creativity in Electronics (ACE) awards ceremony, for his invention of a novel transistor structure. His […]

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