Data indicates that fully-depleted (FD) SOI offers an ideal combination for achieving ultra-low-power, high-performance and cost-effective manufacturability. Companies in the SOI Consortium are working together on furthering the development and technology evaluations. February Results at the Circuit Level A group of companies within the SOI Consortium (ARM, Global Foundries, IBM, SOITEC, ST and Leti), have …

For those new to FD-SOI, here’s a short description of the basic principles. FD SOI transistors are constructed on an ultrathin Silicon layer (< 10nm) set on the top of an ultra-thin BOX (thickness <20nm). This architecture represents a fundamental difference from previous generations of SOI and offers a distinct improvement in power, performance and …

Following the April 2011 VLSI-TSA and VLSI-DAT conferences in Hsinchu, Taiwan, the SOI Consortium hosted the fifth in its series of FD-SOI Workshops. All the presentations (as well as presentations from the previous workshops) can be downloaded from the Consortium website. Here are brief summaries. Introduction (by Horacio Mendez, SOI Consortium): gives an overview of …

One of the key projects currently underway within the SOI Consortium is to understand and provide guidance on the advantages and obstacles of porting SoC designs from Bulk to FD-SOI. This project represents a strategic opportunity to help drive the profile of FD SOI and participate in the emergence of this important technology. Objective: Analyze …

At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights. The roadmap for FD-SOI architectures requires SOI wafer structures with ultra-thin top silicon and ultra-thin insulating BOX (Xtreme SOI TM). Using our industry-standard Smart CutTM technology, Soitec is ramping these wafers in production …

Microsoft and IBM moved the CPU and the GPU of the best-selling game console in North America onto a single SoC – a year ahead of the pack. There’s a lot of excitement about the “latest trend” of integrating both the computing chip – the CPU and the graphics chip – the GPU – into …

Deeply scaled PD- and FD-SOI require new approaches to ESD protection.  Recent work from Stanford and GlobalFoundries on gate controlled FEDs shows great promise. Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits mainly by reducing MOSFET oxide and junction breakdown voltage, diode current shunting capability, and by increasing the interconnect resistivity. …

SOI is at the heart of silicon photonics. Here’s an overview of past, present and future trends. The existence of Silicon Photonics owes much to serendipity. During the early years of the development of SOI wafer technology probably nobody anticipated that SOI would be a perfect medium for short distance transmission and modulation of light …

Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more. Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production …

ST’s newest SOI-based smart power technology delivers big reductions in power consumption in medical equipment, hybrid-electric-vehicle chargers and more. There is an urgent need for semiconductor technologies that can drastically reduce electrical energy consumption in consumer and industrial appliances. At STMicroelectronics, we have developed new SOI-based smart power technology that will make a significant difference …