ASN

Archive of ASN #10

3D ICs: Opportunities & Timing Thumbnail

3D ICs: Opportunities & Timing

Posted by (Yole Développement) on August 16, 2008
In ASN #10, News & Viewpoints, SOI In Action
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A new study from Yole on 3D ICs sees a bright future for applications, markets and active layer transfer technology. Chip performance, size and functionality – especially for consumer electronics – will drive the industry to adopt 3D stacked chips with through-silicon vias (TSVs) replacing wire bonding for certain markets in the 2009-2015 time frame. […]

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The GSA/SOI Industry Consortium Survey Thumbnail

The GSA/SOI Industry Consortium Survey

Posted on July 16, 2008
In ASN #10, News & Viewpoints, SOI In Action
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The “SOI Technology: Semiconductor Perception & Awareness Study” should change the way the industry thinks about SOI. According to an SOI Industry Consortium and GSA survey, SOI is a real, here-and-now solution for the industry’s most pressing challenge: lowering power consumption.

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2008: ARM Lays the SOI Foundation Thumbnail

2008: ARM Lays the SOI Foundation

Posted by (ARM) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
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This fall, ARM will be rolling out key physical IP libraries, opening the door to broad SOI adoption. As the leading processor IP company, ARM is collaborating with industry partners to facilitate the adoption of SOI CMOS technology. ARM’s optimized SOI Physical IP libraries target development of high-speed and low dynamicpower SoC designs in 45nm […]

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Chip Designers: Having It All Thumbnail

Chip Designers: Having It All

Posted by (Synopsys) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
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With SOI, the performance-power trade-off can be balanced without changing design methodology. If you’re a chip designer, what would it mean if you could measurably increase performance while keeping the same power consumption? Or, if you could meaningfully lower power consumption while retaining the same performance level? And what if you could do either one […]

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Calibre Adapts Easily to SOI Thumbnail

Calibre Adapts Easily to SOI

Posted by (Mentor Graphics) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
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How tools from Mentor keep SOI transparent for design; flexible and robust for tapeout. The Mentor Graphics Calibre® nm Platform is built to provide maximum flexibility for designers and tapeout managers employing multiple technologies in their overall IC portfolio. Although SOI requires substantially different and somewhat more complex design rules compared to bulk CMOS, they […]

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Analog Circuit Design in SOI Thumbnail

Analog Circuit Design in SOI

Posted by (IBM) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
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SOI provides key advantages for analog designers. Here’s how and why. Many technical studies have shown that SOI CMOS technology offers substantial digital circuit performance improvements over bulk CMOS at the same lithography node. As more CMOS fabs transition to SOI to enable these gains, analog circuit designers are faced with the task of accommodating […]

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Soitec Names Paul Boudre COO Thumbnail

Soitec Names Paul Boudre COO

Posted on July 16, 2008
In ASN #10, In & Around Our Industry, People
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With promotion from EVP Sales & Marketing, industry veteran also takes on operations. Paul Boudre has been appointed Chief Operating Officer (COO) of SOI wafer-leader Soitec. He first joined joined Soitec’s executive team in January 2007 as a core member of the office of the president, moving into the position of Executive Vice President of […]

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Tony Denayer New CEO at Cissoid Thumbnail

Tony Denayer New CEO at Cissoid

Posted on July 16, 2008
In ASN #10, In & Around Our Industry, People
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With a new CEO, new round of funding, and new product, customers and distribution, Cissoid is on a roll. Tony Denayer, CEO and Director, Cissoi Cissoid has announced the appointment of Tony Denayer as CEO and Director. He joins the company from AMI Semiconductor. Cissoid recently completed a second round of investment with initial investors […]

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Victor Koldyaev Is Innovative Silicon’s First Fellow Thumbnail

Victor Koldyaev Is Innovative Silicon’s First Fellow

Posted on July 16, 2008
In ASN #10, In & Around Our Industry, People
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Craig Factor named VP legal affairs and general counsel. Z-RAM® developer Innovative Silicon, Inc. (ISi) has named Dr. Victor Koldyaev as the company’s first Innovative Silicon Fellow. Dr. Koldyaev joined ISi in August 2007 as director of device, material science and front end-of-the-line (FEOL) integration, where he is responsible for over-seeing process architecture development for […]

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3D at the Wafer Level

Posted by (Soitec) on July 16, 2008
In Advanced Substrate Corners, ASN #10, R&D/Labnews
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Soitec’s core technologies are building blocks for 3D integration. At the wafer level, molecular bonding techniques and Smart Cut technology add significant value to 3D integration. A good application for these building blocks is backside illuminated image sensors (BIS), which is probably the most mature 3D technology and close to mass production. For standard front […]

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