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Archive of Industry Buzz

IEEE SOI-3D-Subthreshold Conference (SF, Oct. ’14) Call for Papers

Posted on April 9, 2014
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After a very successful first edition in 2013, the 2014 IEEE S3S will take place in San Francisco, 6-9 October, 2014 (click here for details). IEEE S3S combines the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, and adds a parallel track in 3D Integration. The technical sessions will be preceded by […]

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U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials Thumbnail

U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials

Posted on April 9, 2014
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The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates […]

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Tronics Manufactures the First Piezoresistive Nanowire 6DOF Inertial MEMS (SOI) Thumbnail

Tronics Manufactures the First Piezoresistive Nanowire 6DOF Inertial MEMS (SOI)

Posted on April 9, 2014
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       A year after announcing the industrialization of CEA-Leti’s breakthrough M&NEMS technologies, Tronics has successfully designed and manufactured the first batch of six-degrees-of-freedom (6DOF) MEMS chips, with 3 accelerometers and 3 gyroscopes on a single die (press release here). Built on SOI wafers, with a die size of less than 4mm2, this 6DOF MEMS […]

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SemiWiki: FD-SOI’s the Technology to Continue Moore’s Law

Posted on March 26, 2014
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A new SemiWiki post by Dr. Eric Esteve of IPnest entitled, The Technology to Continue Moore’s Law… (click here to read it) argues that FD-SOI is the right choice.  He explores cost and manufacturing considerations, and looks at the design issues in logic, memories and analog.  A highly recommended read.

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Presentation on Substrates for SOI-FinFETs and FD-SOI by SEH, World Wafer Leader, Posted on weSRCH Thumbnail

Presentation on Substrates for SOI-FinFETs and FD-SOI by SEH, World Wafer Leader, Posted on weSRCH

Posted on March 26, 2014
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(Courtesy: SEH, weSRCH)   A presentation by Shin‐Etsu Handotai (SEH, the world’s largest wafer supplier) detailing the company’s line-up of wafers for FD-SOI and SOI-FinFET is now available on weSRCH (click here to access it). SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since […]

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Eveon and Leti Leverage SOI in Milestone: Fabrication Of Smart Bolus-type Micro-pump for Drug Delivery Thumbnail

Eveon and Leti Leverage SOI in Milestone: Fabrication Of Smart Bolus-type Micro-pump for Drug Delivery

Posted on March 26, 2014
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(Courtesy: CEA-Leti)   Eveon and CEA-Leti have demonstrated liquid-pumping for smart drug delivery in the bolus mode using a silicon-based micro-pump fabricated with a standard MEMS process. (Read full press release here.) The milestone is the first functional micro-pump integration using MEMS standard process on Leti’s 200mm line. It is a result of FluMin3, Eveon […]

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Soitec Semicon Japan Presentation on Substrates for Mobile Era Now On weSRCH Thumbnail

Soitec Semicon Japan Presentation on Substrates for Mobile Era Now On weSRCH

Posted on March 19, 2014
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  (Image courtesy: SEMI, Soitec, weSRCH) An excellent Soitec presentation from Semicon Japan entitled Innovative Substrates in the Mobile Era is now available on weSRCH (click here to view it). Given by Soitec COO Paul Boudre, it details the role of SOI wafers in RF and FD-SOI for mobile.

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Semicon Europa 2014 Comes to Grenoble, Issues Call for Papers Thumbnail

Semicon Europa 2014 Comes to Grenoble, Issues Call for Papers

Posted on March 19, 2014
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For the first time, SEMICON Europa will be held in Grenoble, France. The greater Grenoble region is home to industry leaders leveraging and researching SOI and related advanced substrates, including Soitec, Leti and  ST. SEMI has now announced the “Call for Papers” for technical sessions and presentations for SEMICON Europa 2014, which takes place October […]

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ST Article in EETimes Details How FD-SOI Supports Moore’s Law Thumbnail

ST Article in EETimes Details How FD-SOI Supports Moore’s Law

Posted on March 19, 2014
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  A powerful, detailed article in EETimes-Asia details how FD-SOI Supports Moore’s Law (click here to read it).  Written by Laurent Remont, ST’s VP and GM for Technology and Product Strategy, Embedded Processing Solutions, it explores FD-SOI’s advantages in terms of price, power and performance versus planar bulk CMOS and FinFETs and 28nm and 14nm. Remont […]

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Soitec article in GSA Forum explores FD-SOI, industry roadmaps

Posted on February 28, 2014
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Soitec Sr. VP (and FD-SOI wafer guru) Christophe Maleville has written a very good, high-level piece in the Global Semiconductor Alliance (GSA) Forum.  Entitled Technology Selection Implications Intensify and Options are Limited, the piece examines cost-per-gate trends and explores roadmap options. He shows how FD-SOI provides a path forward with continued scalability, significant cost advantage […]

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