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Archive of In & Around Our Industry

Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend? Thumbnail

Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend?

Posted by on April 30, 2014
In Design & Manufacturing, News & Viewpoints
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By Ali Khakifirooz (Spansion) One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward […]

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Interview: Peregrine’s new Marketing VP on Global 1®, RF-SOI drivers, UltraCMOS 10 Thumbnail

Interview: Peregrine’s new Marketing VP on Global 1®, RF-SOI drivers, UltraCMOS 10

Posted on April 25, 2014
In Design & Manufacturing, End-User Apps
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Interview with : Duncan Pilgrim, VP of marketing ASN had a chance to catch up with Duncan Pilgrim, Peregrine Semi’s new VP of Marketing. Here he shares insights into the company’s new reconfigurable RF front end. Duncan Pilgrim is the VP of marketing at Peregrine Semiconductor. A 17-year semiconductor industry veteran, he previously served as VP […]

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Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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FD-SOI: Back to Basics for Best Cost, Energy Efficiency and Performance Thumbnail

FD-SOI: Back to Basics for Best Cost, Energy Efficiency and Performance

Posted by and on March 26, 2014
In Design & Manufacturing, News & Viewpoints
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By Bich-Yen Nguyen and Christophe Maleville (Soitec) We are in the era of mobile computing with smart handheld devices and remote data storage “in the cloud,” with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life.  With all the ambitious requirements for better […]

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Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets Thumbnail

Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets

Posted by on March 19, 2014
In Design & Manufacturing, News & Viewpoints
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By Handel Jones IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry.  The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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IP for FD-SOI: Examples from ST Thumbnail

IP for FD-SOI: Examples from ST

Posted by on February 14, 2014
In Design & Manufacturing, Editor's Blog
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Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog. Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here […]

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FD-SOI Opportunities in China Thumbnail

FD-SOI Opportunities in China

Posted by on February 5, 2014
In Design & Manufacturing, News & Viewpoints, Professor's Perspective
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Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS) The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment. The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in […]

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Soitec’s New eSI SOI Wafers For 4G/LTE (Now in High Volume Production) Used at Most Leading RF Foundries Thumbnail

Soitec’s New eSI SOI Wafers For 4G/LTE (Now in High Volume Production) Used at Most Leading RF Foundries

Posted by and on December 5, 2013
In Design & Manufacturing, In & Around Our Industry
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Soitec has reached high-volume manufacturing of our new Enhanced Signal Integrity™ (eSI) substrates, enabling cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production, and are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications. […]

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SOITEC and UCL boost the RF performance of SOI substrates Thumbnail

SOITEC and UCL boost the RF performance of SOI substrates

Posted by and (Soitec) on December 4, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, Professor's Perspective, R&D/Labnews
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Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of […]

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