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Archive of In & Around Our Industry

Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest Thumbnail

Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest

Posted by on October 14, 2013
In Design & Manufacturing, Editor's Blog
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Another RF-SOI solution is making headlines. Leveraging SOI, Toshiba has announced an SP10T RF antenna switch for the smartphone market. The company says it achieves the industry’s lowest insertion loss and smallest size. The company credits its new generation TaRF5 process, the latest in its line of Toshiba-original TarfSOI™ (Toshiba advanced RF SOI) processes. The […]

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Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing Thumbnail

Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing

Posted by (Peregrine Semiconductor) on May 27, 2013
In Design & Manufacturing, In & Around Our Industry, SOI In Action
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For more than 20 years, Silicon-on-Sapphire (SOS) technology—an advanced form of Silicon-on-Insulator (SOI) processing—has been used in semiconductor manufacturing. Recently, SOS in the form of UltraCMOS® technology has been designed into high-volume applications that have made it the technology of choice for several demanding RF applications. This technology combines a highly resistive substrate with CMOS […]

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IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI Thumbnail

IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI

Posted by (IBM) on April 18, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
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Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, […]

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GF’s Two Flavors of FD-SOI – Kengeri Explains (Exclusive ASN Q&A) Thumbnail

GF’s Two Flavors of FD-SOI – Kengeri Explains (Exclusive ASN Q&A)

Posted on April 15, 2013
In Design & Manufacturing, In & Around Our Industry
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Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture. What do you see as the FD-SOI benefits for chip designers? Lower SRAM Vmin for retention and lower operating Vmin […]

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IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value Thumbnail

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value

Posted by (IBM) on November 30, 2012
In Advanced Substrate Corners, ASN #20, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
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FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, […]

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Which wafers for energy-efficient, fully-depleted transistor technologies? Thumbnail

Which wafers for energy-efficient, fully-depleted transistor technologies?

Posted by (Soitec) on November 21, 2012
In ASN #20, Design & Manufacturing, In & Around Our Industry
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To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher […]

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Go Ahead – Take 28nm FD-SOI Out for a Test Drive Thumbnail

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

Posted by on October 31, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes. What would a port to 28nm FD-SOI do for your design? A recent announcement by […]

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Wafer Leaders Extend Basis for Global SOI Supply Thumbnail

Wafer Leaders Extend Basis for Global SOI Supply

Posted by on October 10, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation. SEH is a $12.7 billion company, supplying over 20% of the […]

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET Thumbnail

Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

Posted by (Soitec) on April 20, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of […]

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