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Archive of In & Around Our Industry

Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets Thumbnail

Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets

Posted by on March 19, 2014
In Design & Manufacturing, News & Viewpoints
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By Handel Jones IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry.  The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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IP for FD-SOI: Examples from ST Thumbnail

IP for FD-SOI: Examples from ST

Posted by on February 14, 2014
In Design & Manufacturing, Editor's Blog
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Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog. Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here […]

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FD-SOI Opportunities in China Thumbnail

FD-SOI Opportunities in China

Posted by on February 5, 2014
In Design & Manufacturing, News & Viewpoints, Professor's Perspective
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Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS) The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment. The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in […]

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Soitec’s New eSI SOI Wafers For 4G/LTE (Now in High Volume Production) Used at Most Leading RF Foundries Thumbnail

Soitec’s New eSI SOI Wafers For 4G/LTE (Now in High Volume Production) Used at Most Leading RF Foundries

Posted by and on December 5, 2013
In Design & Manufacturing, In & Around Our Industry
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Soitec has reached high-volume manufacturing of our new Enhanced Signal Integrity™ (eSI) substrates, enabling cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production, and are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications. […]

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SOITEC and UCL boost the RF performance of SOI substrates Thumbnail

SOITEC and UCL boost the RF performance of SOI substrates

Posted by and (Soitec) on December 4, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, Professor's Perspective, R&D/Labnews
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Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of […]

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FinFET on SOI: Potential Becomes Reality Thumbnail

FinFET on SOI: Potential Becomes Reality

Posted by on November 26, 2013
In Design & Manufacturing, In & Around Our Industry
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Authors: T. B. Hook, I. Ahsan, A. Kumar, K. McStay, E. Nowak, S. Saroop, C. Schiller, G. Starkey, IBM Semiconductor Research and Development Center We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions.  However, […]

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Back-biasing for FD-SOI – a simple way to meet power/performance targets Thumbnail

Back-biasing for FD-SOI – a simple way to meet power/performance targets

Posted by on November 2, 2013
In Design & Manufacturing, Editor's Blog
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FD-SOI with back-biasing* (BB – also referred to as body-biasing) is an immensely powerful tool, especially for getting great performance at very low voltages with extremely low leakage. Implemented on a smartphone processor, it’s what would give you that extra day of battery life or get you to 3GHz. But what does it mean for […]

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Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest Thumbnail

Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest

Posted by on October 14, 2013
In Design & Manufacturing, Editor's Blog
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Another RF-SOI solution is making headlines. Leveraging SOI, Toshiba has announced an SP10T RF antenna switch for the smartphone market. The company says it achieves the industry’s lowest insertion loss and smallest size. The company credits its new generation TaRF5 process, the latest in its line of Toshiba-original TarfSOI™ (Toshiba advanced RF SOI) processes. The […]

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Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing Thumbnail

Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing

Posted by (Peregrine Semiconductor) on May 27, 2013
In Design & Manufacturing, In & Around Our Industry, SOI In Action
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For more than 20 years, Silicon-on-Sapphire (SOS) technology—an advanced form of Silicon-on-Insulator (SOI) processing—has been used in semiconductor manufacturing. Recently, SOS in the form of UltraCMOS® technology has been designed into high-volume applications that have made it the technology of choice for several demanding RF applications. This technology combines a highly resistive substrate with CMOS […]

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