ASN

Archive of In & Around Our Industry

Opening the Route for Wireless SOI Systems-On-Chip Thumbnail

Opening the Route for Wireless SOI Systems-On-Chip

Posted by (Cissoid) on April 6, 2006
In ASN #4, Design & Manufacturing, In & Around Our Industry
Tagged with , , , ,

Optimization of RF circuits for high-resistivity SOI substrates facilitates multi-mode, multi-standard terminals integration. The new generations of multi-mode, multistandards terminals increase the need to integrate digital, analog and RF functions on the same substrates using a System-on- Chip (SoC) approach. Silicon-on-Insulator (SOI), which can use high-resistivity (HR) wafers ( > 1000 ohms.cm) for the mechanical, […]

Continue ReadingLeave a Comment
Fab Floor Tip: Running SOI in RTP Thumbnail

Fab Floor Tip: Running SOI in RTP

Posted by (Soitec) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
Tagged with , , ,

A quick guide to successful rapid thermal processing of SOI wafers Some engineers have indicated that they encounter challenges when running SOI wafers in rapid thermal processing (RTP). Why is this specific to SOI?

Continue ReadingLeave a Comment
Achieving High Throughput Inspection of Multiple SOI Wafers Thumbnail

Achieving High Throughput Inspection of Multiple SOI Wafers

Posted by (KLA Tencor) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
Tagged with , , , ,

Historically, chipmakers conducting incoming quality control (IQC) on SOI wafers used for advanced logic devices are challenged in inspecting these substrates as efficiently and effectively as their bulk counterparts. The prevailing inspection process utilizes visible light inspection systems. However, these systems often require specific recipe setups and tool calibrations for each SOI wafer type and […]

Continue ReadingLeave a Comment

Soitec and SEZ Collaborate to Speed Industrialization of sSOI

Posted on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
Tagged with , , , ,

Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production   Soitec and SEZ have initiated a joint development program intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates. The goal is to develop new wet-etch processes designed to optimize total germanium removal in […]

Continue ReadingLeave a Comment
NIST Nanowire Transistors on SOI Thumbnail

NIST Nanowire Transistors on SOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
Tagged with ,

New design simplifies processing and on/off switching Using SOI as the substrate, researchers at the National Institute of Standards and Technology (NIST) have overcome some of the main challenges to making silicon nanowire devices. As noted in the journal “Nanotechnology” (June, 2005), the NIST design uses a simplified type of contact between the nanowire channel […]

Continue ReadingLeave a Comment
MIRAI-ASET Working on SGOI and GeOI Thumbnail

MIRAI-ASET Working on SGOI and GeOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
Tagged with ,

3,1 times greater hole-mobility observed in ultra-thin GeOI   MIRAI-ASET, a government-sponsored Japanese research consortium, has been working on SGOI (SiGe on Insulator) and GeOI (Germanium on Insulator) for high-performance CMOS. Recent findings were reported at the last International Conference on Solid State Devices and Materials (S.Nakaharai et al.; SSDM 2005, pp.868-869, Kobe, Japan). They […]

Continue ReadingLeave a Comment
Soitec President Elected to SEMI Board Thumbnail

Soitec President Elected to SEMI Board

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, People
Tagged with

Auberton-Hervé joins other prominent industry leaders in representing the interests of material suppliers and equipment manufacturers   SEMI recently announced the appointment of André-Jacques Auberton-Hervé to its International Board of Directors. Auberton-Hervé was unanimously elected by the 20 voting members of the association’s board at its recent annual policy and planning meeting. In his announcement, […]

Continue ReadingLeave a Comment
New Textbook on FD-SOI Circuit Technology from Springer Thumbnail

New Textbook on FD-SOI Circuit Technology from Springer

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, People
Tagged with , , , , ,

31 of Japan’s leading SOI experts explain design for ultra-low-power applications   Leading experts expect the next-generation of device technology for ultra-low-power applications to be based on FD (fully-depleted) SOI MOSFETs. For circuit designers and university students who would like to learn about FD-SOI design, and get a basic understanding of the material technology and […]

Continue ReadingLeave a Comment
First ASIC design kit for 90nm SOI process Thumbnail

First ASIC design kit for 90nm SOI process

Posted by (Soisic) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
Tagged with , ,

Soisic solution enables any ASIC designer using industry-standard EDA tools to move transparently into SOI     Until now, any company doing SOI chips has been using their own internal tools and design flows: there was no standard SOI ASIC design kit available. This effectively shut out fabless companies and complicated things for those companies […]

Continue ReadingLeave a Comment
Just 0.3V operating voltage for Seiko Instruments Inc.’s charge-pumping FD-SOI IC Thumbnail

Just 0.3V operating voltage for Seiko Instruments Inc.’s charge-pumping FD-SOI IC

Posted on December 7, 2005
In Advanced Substrate Corners, ASN #3, Power
Tagged with ,

www.sii-ic.com SII’s new chip can leverage energy sources such as personal body-heat or natural illumination   SII (Seiko Instruments Inc., Japan) has successfully developed a charge-pumping IC that can operate on a minimum input voltage of just 0.3 volts.

Continue ReadingLeave a Comment