Ongoing since 2002, the MEDEA+ T206 CMOS SOI project is scheduled to finish up this September. The objective is: “…to evaluate, design and manufacture a family of CMOS silicon-on- insulator (SOI) circuits for low-power portable, radio frequency (RF) wireless and high-speed applications to compete with more expensive CMOS and bipolar CMOS (BiCMOS) devices.” The program, …

In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar …

Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electrical and physico-chemical tests such as Psi-Mos, Hg-fet, CV, Box integrity, BMD and SECCO on SOI, sSOI and new materials. R&D researchers in the lab are developing new characterization techniques for future needs. The lab is audited regularly by customers, …

A preliminary public version of the “EUROSOI State of the Art Report” is now available at www.eurosoi.org. It compiles the contributions of more than 150 researchers/experts from 14 European countries active in SOI technology, devices and systems. A listing of current European and national SOI projects is also available on the site •

SOI pioneer Jerry G. Fossum has received the most recent J.J. Ebers award, “For outstanding contributions to the advancement of SOI CMOS devices and circuits through modeling.” He thereby joins such industry luminaries as Andrew Grove and Bernard Meyerson in receiving one of the Electron Devices Society’s (EDS) and IEEE’s highest honors.

A new book, SOI Device Technology by Makoto Yoshimi, PhD, covers the history of SOI, the floating body effect and a variety of LSI applications. An SOI pioneer (he began his research over 20 years ago for Toshiba), Makoto Yoshimi is now Chief Scientist of Soitec Asia. “This book describes what SOI is all about”, …

Here’s a quick review of some recent Smart Cut activity. March 2005 – WORLD’S FIRST GALLIUM NITRIDE (GaN)-ON- INSULATOR SUBSTRATE Soitec announced that its Smart Cut technology was used to split and transfer a thin layer of GaN from a high-quality GaN donor wafer onto a carrier wafer— generating the world’s first single- crystal, thin-film …

While microelectronics relies on SOI for its insulating layer, SOI-MEMS benefits from the single crystal silicon of the top layer and substrate. A good example is the latest product from TRONIC’S Microsystems, a French manufacturer of high-end custom components. The geophone, a seismic vibration sensor manufactured for Sercel (the world leader in oil exploration equipment), …

SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already proven their performance advantage in CPU applications. When compared with bulk CMOS at same power-supply voltage (Vdd) and same leakage current, SOI delivers a higher speed thanks to: • the combination of a lower junction …