ASN

Archive of In & Around Our Industry

EuroSOI Gears Up for Next Programme Thumbnail

EuroSOI Gears Up for Next Programme

Posted on April 6, 2006
In ASN #4, In & Around Our Industry, R&D/Labnews
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Network successfully federating research collaboration. Now entering its third year, the EuroSOI Thematic Network on Silicon on Insulator Technology, Devices and Circuits is delivering on its charter to “federate the existing research network on SOI topics.” It is under the aegis of the European Commission’s research activities, which are structured around consecutive, four-year Framework Programmes […]

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Medea+ sSOI Partners Now Public Thumbnail

Medea+ sSOI Partners Now Public

Posted on April 6, 2006
In ASN #4, In & Around Our Industry, R&D/Labnews
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Program includes AMD, Freescale, Infineon, Philips and ST. The list of partners in the Medea+ Strained Silicon-On-Insulator Substrates for High Performance ICs program, known as SilOnIS, has now been made public. Among the corporate partners are AMD, ASM, Freescale, Infineon, Philips, Siltronic and ST, among others. Lead by Soitec, the project’s stated goal is to […]

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SOI-MEMS Go Straight to the Heart Thumbnail

SOI-MEMS Go Straight to the Heart

Posted on April 6, 2006
In ASN #4, In & Around Our Industry, MEMS
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www.tronics-mst.com www.elamedical.com A European leader in pacemakers relies on SOI based accelerometers to adapt pacing to activity level. On the leading edge of medical technology, accelerometers that detect a person’s activity level are enabling major improvements in pacemakers and other cardiac devices. Pacemakers are used when the heart beats at incorrect levels; but of course, […]

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Cost Impact of Switching From Bulk to SOI Thumbnail

Cost Impact of Switching From Bulk to SOI

Posted by (Soisic) on April 6, 2006
In ASN #4, Design & Manufacturing, In & Around Our Industry
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Overall the cost of an SOI chip is not higher than bulk and may even be lower, depending on the application. Cost is an important factor when developing a chip and going to production. Users of bulk substrates may ask how they can manage the added cost of the SOI substrate if they were to […]

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Opening the Route for Wireless SOI Systems-On-Chip Thumbnail

Opening the Route for Wireless SOI Systems-On-Chip

Posted by (Cissoid) on April 6, 2006
In ASN #4, Design & Manufacturing, In & Around Our Industry
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Optimization of RF circuits for high-resistivity SOI substrates facilitates multi-mode, multi-standard terminals integration. The new generations of multi-mode, multistandards terminals increase the need to integrate digital, analog and RF functions on the same substrates using a System-on- Chip (SoC) approach. Silicon-on-Insulator (SOI), which can use high-resistivity (HR) wafers ( > 1000 ohms.cm) for the mechanical, […]

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Fab Floor Tip: Running SOI in RTP Thumbnail

Fab Floor Tip: Running SOI in RTP

Posted by (Soitec) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
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A quick guide to successful rapid thermal processing of SOI wafers Some engineers have indicated that they encounter challenges when running SOI wafers in rapid thermal processing (RTP). Why is this specific to SOI?

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Achieving High Throughput Inspection of Multiple SOI Wafers Thumbnail

Achieving High Throughput Inspection of Multiple SOI Wafers

Posted by (KLA Tencor) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
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Historically, chipmakers conducting incoming quality control (IQC) on SOI wafers used for advanced logic devices are challenged in inspecting these substrates as efficiently and effectively as their bulk counterparts. The prevailing inspection process utilizes visible light inspection systems. However, these systems often require specific recipe setups and tool calibrations for each SOI wafer type and […]

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Soitec and SEZ Collaborate to Speed Industrialization of sSOI

Posted on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
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Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production   Soitec and SEZ have initiated a joint development program intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates. The goal is to develop new wet-etch processes designed to optimize total germanium removal in […]

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NIST Nanowire Transistors on SOI Thumbnail

NIST Nanowire Transistors on SOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
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New design simplifies processing and on/off switching Using SOI as the substrate, researchers at the National Institute of Standards and Technology (NIST) have overcome some of the main challenges to making silicon nanowire devices. As noted in the journal “Nanotechnology” (June, 2005), the NIST design uses a simplified type of contact between the nanowire channel […]

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MIRAI-ASET Working on SGOI and GeOI Thumbnail

MIRAI-ASET Working on SGOI and GeOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
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3,1 times greater hole-mobility observed in ultra-thin GeOI   MIRAI-ASET, a government-sponsored Japanese research consortium, has been working on SGOI (SiGe on Insulator) and GeOI (Germanium on Insulator) for high-performance CMOS. Recent findings were reported at the last International Conference on Solid State Devices and Materials (S.Nakaharai et al.; SSDM 2005, pp.868-869, Kobe, Japan). They […]

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