ASN

Archive of In & Around Our Industry

First ASIC design kit for 90nm SOI process Thumbnail

First ASIC design kit for 90nm SOI process

Posted by (Soisic) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
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Soisic solution enables any ASIC designer using industry-standard EDA tools to move transparently into SOI     Until now, any company doing SOI chips has been using their own internal tools and design flows: there was no standard SOI ASIC design kit available. This effectively shut out fabless companies and complicated things for those companies […]

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Just 0.3V operating voltage for Seiko Instruments Inc.’s charge-pumping FD-SOI IC Thumbnail

Just 0.3V operating voltage for Seiko Instruments Inc.’s charge-pumping FD-SOI IC

Posted on December 7, 2005
In Advanced Substrate Corners, ASN #3, Power
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www.sii-ic.com SII’s new chip can leverage energy sources such as personal body-heat or natural illumination   SII (Seiko Instruments Inc., Japan) has successfully developed a charge-pumping IC that can operate on a minimum input voltage of just 0.3 volts.

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Self-Powered Short-Range Wireless System with MTCMOS/SOI LSIs Thumbnail

Self-Powered Short-Range Wireless System with MTCMOS/SOI LSIs

Posted by (NTT Corporation) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
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Ultralow-power MTCMOS/SOI technology enables self-powered wireless transmission by just touching a terminal Ultralow-power LSIs with 1- to 10-mW power dissipation should open the way to self-powered short- range wireless systems that use ambient energy sources, such as the light, kinetic and thermal energy sources around us.

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SOI and sSOI Address MPU Clock Speed Challenge

Posted by (Soitec) on July 11, 2005
In ASN #2, Design & Manufacturing, In & Around Our Industry
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IC makers need both local and global strained SOI to win the GHz race. At the device level, the switching speed of MOS logic transistors (gate delay) is limited by two factors: 1. The times required to charge and discharge the parasitic capacitances that exist between electrodes and the body substrate. 2. The transit time […]

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Strain and SOI Lead to Faster, Cooler Transistors Thumbnail

Strain and SOI Lead to Faster, Cooler Transistors

Posted by (Applied Materials) on July 11, 2005
In ASN #2, Design & Manufacturing, In & Around Our Industry
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Applied Materials responds to evolving requirements. Prior to 65nm device manufacturing, performance improvements from one generation to the next have been gained primarily through continuous reduction of transistor dimensions. However, for the 65nm generation and below, following this approach without change leads to unacceptably high leakage and power consumption. To help navigate this formidable challenge […]

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MEDEA+ 2T101: sSOI for High-Performance ICs

Posted on July 11, 2005
In ASN #2, In & Around Our Industry, R&D/Labnews
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The objective is to provide an industrial source of large diameter strained SOI wafers within 3 years. A “Phase 2” MEDEA+ project, 2T101, known as SILONIS is currently ramping up. The project, which is lead by Soitec, involves 15 partners, including suppliers and IC makers active in four different European countries.

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OPTIMUM

Posted on July 11, 2005
In ASN #2, In & Around Our Industry, R&D/Labnews
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Financing approved for new III-V program The first phase of OPTIMUM, a new III-V research project lead by Thales Communications France (TCF) and partners UMS, OMMIC and Picogiga International, has recently been approved and financed. There are four sub-sections within the pro-ject. The first focuses on innovative III-V materials and technologies, in particular the optimization […]

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EE Times Awards AMD, Cites SOI Innovation Thumbnail

EE Times Awards AMD, Cites SOI Innovation

Posted on July 11, 2005
In ASN #2, In & Around Our Industry, People
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Ruiz and AMD are among the first ACE winners. At the first Annual Creativity in Electronics (ACE) Awards, EE Times celebrated the innovative spirit of Hector Ruiz and AMD, awarding them Executive of the Year and Large Company of the Year, respectively. The panel of 18 judges singled out the move to SOI as a […]

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New Edition of SOI Book by J.-P. Colinge

Posted on July 11, 2005
In ASN #2, In & Around Our Industry, People
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Silicon-on-Insulator Technology: Materials to VLSI is now available from Springer. The third edition of Professor Jean-Pierre Colinge’s book, Silicon-on-Insulator Technology: Materials to VLSI (ISBN: 1-4020-7773-4), is now available from www.springeronline.com. A prolific author, Professor Colinge has written a book that covers the history of SOI technology and provides in-depth analyses of the physics, device properties […]

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STRAINED SOI

Posted on July 11, 2005
In ASN #2, Design & Manufacturing, In & Around Our Industry
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APRIL 2005 – FREESCALE AND SOITEC ACHIEVE 70- PERCENT IMPROVEMENT IN ELECTRON MOBILITY USING STRAINED SOI FOR SUB-65-NM DEVICES Freescale and Soitec Group announced the results of their joint development effort to optimize CMOS device performance at the sub-65-nm nodes using strained silicon-on-insulator (sSOI) engineered substrates. With device results revealing an approximate 70-percent increase in […]

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