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Archive of In & Around Our Industry

New Layer Transfer Technology Moves Processed Circuits to the Best Substrates for the Application Thumbnail

New Layer Transfer Technology Moves Processed Circuits to the Best Substrates for the Application

Posted by (Soitec) on May 11, 2007
In ASN #7, Design & Manufacturing, In & Around Our Industry
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Transferring a layer with all the circuits from a processed wafer onto another support substrate decouples the exigencies of circuit fabrication from the needs of the final application. The best substrate for circuit fabrication is not always the best choice for the functioning of the chip. Nor is the best substrate for the final application […]

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Thin BOX: A Solution for High-Speed, Low-Power SoCs Thumbnail

Thin BOX: A Solution for High-Speed, Low-Power SoCs

Posted by (Hitachi) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond. Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node.

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Floating Body RAM Becomes an Industrial Reality Thumbnail

Floating Body RAM Becomes an Industrial Reality

Posted by (Toshiba Corporation) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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Toshiba has successfully developed a high-performance, high-density, low-cost 128Mb FBRAM. FBRAM is Random Access Memory (RAM) with a Floating Body Cell (FBC). It is a capacitor-less DRAM cell consisting of a MOSFET on an SOI wafer. Data “1” and Data “0” are distinguished by the hole density in the floating body of the MOSFET.

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Embedded Memories in SOI Thumbnail

Embedded Memories in SOI

Posted by (IBM) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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Embedded DRAM on SOI is set to proliferate at the 45nm node. Embedded memory now occupies close to 75% of the total chip area. Until a few years ago, this memory was exclusively SRAM, but more recently the industry has seen a significant transition to embedded DRAMs (eDRAMs).

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Harnessing SOI’s Floating Body Effect for Dense Memory Cells Thumbnail

Harnessing SOI’s Floating Body Effect for Dense Memory Cells

Posted by (Innovative Silicon) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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The co-inventor of Z-RAM explains the technology. As a Z-RAM – zero capacitor RAM – memory technology bit cell uses only a transistor plus the floating body effect inherent in SOI processing (see Figure 1), it typically measures only 15-20F² (where F is the technology minimum feature size).

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Ultra-Thin Body & Box (UTB²) SOI Thumbnail

Ultra-Thin Body & Box (UTB²) SOI

Posted by (STMicroelectronics) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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As we approach the end of the roadmap, single gate FD SOI devices with ultra-thin BOX could pre-empt the need for double gate devices. It is well known that UTB (Ultra Thin Body) devices present improved electrostatic integrity. We were, however, among the first to report [1] on the importance of the BOX thickness with […]

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SOI Substrates with Ultra-Thin BOX Thumbnail

SOI Substrates with Ultra-Thin BOX

Posted by (Soitec) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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Soitec is now sampling 25nm-thick UT-BOX. Advanced SOI with ultra thin buried oxide (UT-BOX), in which the insulating BOX layer is less than 50nm thick, brings additional benefits to SOI CMOS architecture. It enables: • electrostatic control of the device by back biasing, allowing ultra-low power operation through dynamic Vt control [1, 2]. • the […]

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Laurent Malier Named CEO of CEA-Leti Thumbnail

Laurent Malier Named CEO of CEA-Leti

Posted on December 6, 2006
In ASN #6, In & Around Our Industry, People
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New leader for one of world’s top microelectronics labs and original home of Smart Cut™ technology. Dr. Laurent Malier has been named as the new CEO of CEA-Leti, one of the world’s leading microelectronics laboratories. Dr. Malier, who holds a PhD in solid state physics, joined Leti two years ago from a major US company […]

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AMD Names Soitec as Best Wafer Fab Materials Supplier Thumbnail

AMD Names Soitec as Best Wafer Fab Materials Supplier

Posted on December 6, 2006
In ASN #6, In & Around Our Industry, People
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World Class Supplier Pathfinder Award recognizes support and commitment. AMD presented its annual WCS Pathfinder Award for Best Wafer Fab Materials Supplier to Soitec during a recent awards banquet in Dresden, Germany, home to AMD’s Fab 30 and AMD Fab 36 manufacturing facilities.

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Simon Deleonibus Recognized as IEEE Fellow Thumbnail

Simon Deleonibus Recognized as IEEE Fellow

Posted on December 6, 2006
In ASN #6, In & Around Our Industry, People
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Leti lab director and inventor of the principle of contact plugs now leveraging advanced substrates. In further recognition of his distinguished career, Dr. Simon Deleonibus, Director of Leti’s Electronic Nanodevices Laboratory, was recently awarded the grade of IEEE Fellow “for contributions to nanoscaled CMOS devices technology”. This follows on other recent awards including the Grand […]

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