Silicon-on-Insulator Technology: Materials to VLSI is now available from Springer. The third edition of Professor Jean-Pierre Colinge’s book, Silicon-on-Insulator Technology: Materials to VLSI (ISBN: 1-4020-7773-4), is now available from www.springeronline.com. A prolific author, Professor Colinge has written a book that covers the history of SOI technology and provides in-depth analyses of the physics, device properties …

APRIL 2005 – FREESCALE AND SOITEC ACHIEVE 70- PERCENT IMPROVEMENT IN ELECTRON MOBILITY USING STRAINED SOI FOR SUB-65-NM DEVICES Freescale and Soitec Group announced the results of their joint development effort to optimize CMOS device performance at the sub-65-nm nodes using strained silicon-on-insulator (sSOI) engineered substrates. With device results revealing an approximate 70-percent increase in …

Z-RAM + SOI can save > 40%. There is no doubt today that the industry, led by the microprocessor segment, is moving to take advantage of the lower power consumption and higher performance of SOI compared to bulk wafers.

When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These capacitive and resistive losses negatively impact energy management. The semiconducting properties of the silicon also induce transmission of parasitic interferences (crosstalk) (see Figure 1). Usage of an SOI substrate improves …

Ongoing since 2002, the MEDEA+ T206 CMOS SOI project is scheduled to finish up this September. The objective is: “…to evaluate, design and manufacture a family of CMOS silicon-on- insulator (SOI) circuits for low-power portable, radio frequency (RF) wireless and high-speed applications to compete with more expensive CMOS and bipolar CMOS (BiCMOS) devices.” The program, …

In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar …

Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electrical and physico-chemical tests such as Psi-Mos, Hg-fet, CV, Box integrity, BMD and SECCO on SOI, sSOI and new materials. R&D researchers in the lab are developing new characterization techniques for future needs. The lab is audited regularly by customers, …

A preliminary public version of the “EUROSOI State of the Art Report” is now available at www.eurosoi.org. It compiles the contributions of more than 150 researchers/experts from 14 European countries active in SOI technology, devices and systems. A listing of current European and national SOI projects is also available on the site •

SOI pioneer Jerry G. Fossum has received the most recent J.J. Ebers award, “For outstanding contributions to the advancement of SOI CMOS devices and circuits through modeling.” He thereby joins such industry luminaries as Andrew Grove and Bernard Meyerson in receiving one of the Electron Devices Society’s (EDS) and IEEE’s highest honors.

A new book, SOI Device Technology by Makoto Yoshimi, PhD, covers the history of SOI, the floating body effect and a variety of LSI applications. An SOI pioneer (he began his research over 20 years ago for Toshiba), Makoto Yoshimi is now Chief Scientist of Soitec Asia. “This book describes what SOI is all about”, …