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Archive of Design & Manufacturing

Strain and SOI Lead to Faster, Cooler Transistors Thumbnail

Strain and SOI Lead to Faster, Cooler Transistors

Posted by Randhir THAKUR (Applied Materials) on July 11, 2005
In ASN #2, Design & Manufacturing, In & Around Our Industry
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Applied Materials responds to evolving requirements. Prior to 65nm device manufacturing, performance improvements from one generation to the next have been gained primarily through continuous reduction of transistor dimensions. However, for the 65nm generation and below, following this approach without change leads to unacceptably high leakage and power consumption. To help navigate this formidable challenge …

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STRAINED SOI

Posted on July 11, 2005
In ASN #2, Design & Manufacturing, In & Around Our Industry
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APRIL 2005 – FREESCALE AND SOITEC ACHIEVE 70- PERCENT IMPROVEMENT IN ELECTRON MOBILITY USING STRAINED SOI FOR SUB-65-NM DEVICES Freescale and Soitec Group announced the results of their joint development effort to optimize CMOS device performance at the sub-65-nm nodes using strained silicon-on-insulator (sSOI) engineered substrates. With device results revealing an approximate 70-percent increase in …

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Zero Capacitor Embedded Memory Technology Reverses SOI vs. Bulk Economics Thumbnail

Zero Capacitor Embedded Memory Technology Reverses SOI vs. Bulk Economics

Posted by Mark-Eric JONES (Innovative Silicon) on July 11, 2005
In ASN #2, Design & Manufacturing, In & Around Our Industry
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Z-RAM + SOI can save > 40%. There is no doubt today that the industry, led by the microprocessor segment, is moving to take advantage of the lower power consumption and higher performance of SOI compared to bulk wafers.

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SOI for RF & Low Power ICs Thumbnail

SOI for RF & Low Power ICs

Posted by Christophe DESRUMAUX (Soitec) on April 18, 2005
In ASN #1, Design & Manufacturing, In & Around Our Industry
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When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These capacitive and resistive losses negatively impact energy management. The semiconducting properties of the silicon also induce transmission of parasitic interferences (crosstalk) (see Figure 1). Usage of an SOI substrate improves …

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WORLD’S FIRST GaN-ON-INSULATOR

Posted on April 18, 2005
In ASN #1, Design & Manufacturing, In & Around Our Industry
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Here’s a quick review of some recent Smart Cut activity. March 2005 – WORLD’S FIRST GALLIUM NITRIDE (GaN)-ON- INSULATOR SUBSTRATE Soitec announced that its Smart Cut technology was used to split and transfer a thin layer of GaN from a high-quality GaN donor wafer onto a carrier wafer— generating the world’s first single- crystal, thin-film …

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How to Use SOI for Low-Power Applications Thumbnail

How to Use SOI for Low-Power Applications

Posted by Jean-Luc PELLOIE (Soisic) on April 18, 2005
In ASN #1, Design & Manufacturing, In & Around Our Industry
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SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already proven their performance advantage in CPU applications. When compared with bulk CMOS at same power-supply voltage (Vdd) and same leakage current, SOI delivers a higher speed thanks to: • the combination of a lower junction …

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