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Archive of Design & Manufacturing

EVG Takes on 450 mm and SOI with Newest Wafer-Bonding System Thumbnail

EVG Takes on 450 mm and SOI with Newest Wafer-Bonding System

Posted by (EV Group) on October 28, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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EVG’s new wafer bonding system is a fully automated tool for production-level fabrication of 450mm SOI wafers. Transitioning to larger wafers heightens the need for process uniformity.  Wafer bonding is no exception, as process parameters must be applied with a high degree of both precision and uniformity.  This requirement will become particularly critical within the […]

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FD-SOI: The Substrates Are Ready Thumbnail

FD-SOI: The Substrates Are Ready

Posted by (Soitec) on May 25, 2011
In ASN #17, Design & Manufacturing, In & Around Our Industry, Power
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At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights. The roadmap for FD-SOI architectures requires SOI wafer structures with ultra-thin top silicon and ultra-thin insulating BOX (Xtreme SOI TM). Using our industry-standard Smart CutTM technology, Soitec is ramping these wafers in production […]

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ESD Protection for Advanced SOI Thumbnail

ESD Protection for Advanced SOI

Posted by (GlobalFoundries) on May 4, 2011
In ASN #17, Design & Manufacturing, In & Around Our Industry
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Deeply scaled PD- and FD-SOI require new approaches to ESD protection.  Recent work from Stanford and GlobalFoundries on gate controlled FEDs shows great promise. Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits mainly by reducing MOSFET oxide and junction breakdown voltage, diode current shunting capability, and by increasing the interconnect resistivity. […]

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What Smart Stacking™ can do for you Thumbnail

What Smart Stacking™ can do for you

Posted by (Soitec) on April 22, 2011
In ASN #17, Design & Manufacturing, Imaging, In & Around Our Industry, MEMS
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Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more. Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production […]

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Wafers for Fully Depleted SOI Devices: Ready for Volume Thumbnail

Wafers for Fully Depleted SOI Devices: Ready for Volume

Posted by (Soitec) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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A technological tour-de-force, Soitec’s wafers for FD SOI meet all the requirements At the 20 nm node, short channel effects and random dopant fluctuations (RDF) are the major hurdles facing the CMOS industry. An extremely attractive solution is the planar, ultra-thin body Fully-Depleted (FD) SOI transistor. These devices are built on an ultra-thin SOI substrate, […]

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Right Timing Thumbnail

Right Timing

Posted by (ARM) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models. SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each […]

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Conquering Convergence Thumbnail

Conquering Convergence

Posted by and (STMicroelectronics) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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ST looks at a hybrid FD-SOI/bulk approach to SOCs for multimedia. The heterogeneous nature of System-on-Chip (SOC) design for the next generations of wireless, high-performance, low-power multimedia applications makes it a complex balancing act. Our research indicates that a hybrid FD-SOI/Bulk, high-k/metal-gate platform is an excellent candidate for such applications, most probably around the 22nm […]

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ETSOI Substrates: What We Needi Thumbnail

ETSOI Substrates: What We Needi

Posted by (IBM) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why. ETSOI transistors are thin-channel planar devices. Halo implantation is used to control electrostatics in conventional transistors. Although the halo controls the short channel effects, it also causes large random doping fluctuations and increases junction […]

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Model Behavior Thumbnail

Model Behavior

Posted by (CEA-Leti) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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Leti has compact models ready for FD-SOI SPICE simulations. A critical link in the move to FD-SOI is the availability of robust compact models. Compact models of transistors and other elementary devices are used to predict the behavior of a design.  As such, they are embedded in simulations like SPICE that designers run before actual […]

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Using FD-SOI to Design Competitive Chips Thumbnail

Using FD-SOI to Design Competitive Chips

Posted by (Soitec) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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FD-SOI solves challenges without complicating design and manufacturing. Designing a successful consumer-type IC requires a balanced combination of: packing in more differentiating features, reaching good performance with low power, keeping final application costs competitive, and respecting time-to-market. Figure 1 illustrates how just a few key features intrinsic to FD-SOI translate into advantages that serve those […]

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