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Which wafers for energy-efficient, fully-depleted transistor technologies? Thumbnail

Which wafers for energy-efficient, fully-depleted transistor technologies?

Posted by (Soitec) on November 21, 2012
In ASN #20, Design & Manufacturing, In & Around Our Industry
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To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher […]

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET Thumbnail

Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

Posted by (Soitec) on April 20, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of […]

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ST: FD-SOI for Competitive SOCs at 28nm and Beyond Thumbnail

ST: FD-SOI for Competitive SOCs at 28nm and Beyond

Posted by (STMicroelectronics) on November 18, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics sees its flavor of planar FD-SOI as an excellent response to the complex needs of mobile multimedia chips. The multi-functional system-on-chips (SOC) needed at the heart of the next generations of wireless, high-performance, low-power multimedia devices have very different needs than the mono-functional processors of the past. Traditionally, the trade-off for computers and servers […]

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Bulk logic designs for mobile apps port directly to FD-SOI Thumbnail

Bulk logic designs for mobile apps port directly to FD-SOI

Posted by (ARM) on November 4, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of […]

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EVG Takes on 450 mm and SOI with Newest Wafer-Bonding System Thumbnail

EVG Takes on 450 mm and SOI with Newest Wafer-Bonding System

Posted by (EV Group) on October 28, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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EVG’s new wafer bonding system is a fully automated tool for production-level fabrication of 450mm SOI wafers. Transitioning to larger wafers heightens the need for process uniformity.  Wafer bonding is no exception, as process parameters must be applied with a high degree of both precision and uniformity.  This requirement will become particularly critical within the […]

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FD-SOI: The Substrates Are Ready Thumbnail

FD-SOI: The Substrates Are Ready

Posted by (Soitec) on May 25, 2011
In ASN #17, Design & Manufacturing, In & Around Our Industry, Power
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At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights. The roadmap for FD-SOI architectures requires SOI wafer structures with ultra-thin top silicon and ultra-thin insulating BOX (Xtreme SOI TM). Using our industry-standard Smart CutTM technology, Soitec is ramping these wafers in production […]

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ESD Protection for Advanced SOI Thumbnail

ESD Protection for Advanced SOI

Posted by (GlobalFoundries) on May 4, 2011
In ASN #17, Design & Manufacturing, In & Around Our Industry
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Deeply scaled PD- and FD-SOI require new approaches to ESD protection.  Recent work from Stanford and GlobalFoundries on gate controlled FEDs shows great promise. Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits mainly by reducing MOSFET oxide and junction breakdown voltage, diode current shunting capability, and by increasing the interconnect resistivity. […]

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What Smart Stacking™ can do for you Thumbnail

What Smart Stacking™ can do for you

Posted by (Soitec) on April 22, 2011
In ASN #17, Design & Manufacturing, Imaging, In & Around Our Industry, MEMS
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Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more. Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production […]

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Wafers for Fully Depleted SOI Devices: Ready for Volume Thumbnail

Wafers for Fully Depleted SOI Devices: Ready for Volume

Posted by (Soitec) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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A technological tour-de-force, Soitec’s wafers for FD SOI meet all the requirements At the 20 nm node, short channel effects and random dopant fluctuations (RDF) are the major hurdles facing the CMOS industry. An extremely attractive solution is the planar, ultra-thin body Fully-Depleted (FD) SOI transistor. These devices are built on an ultra-thin SOI substrate, […]

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