ASN

Archive of Design & Manufacturing

Fully Depleted (FD) SOI for the Next Generation Thumbnail

Fully Depleted (FD) SOI for the Next Generation

Posted by on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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FD-SOI is making the move towards industrialization. In this issue of ASN, experts from IBM, ST, Hitachi, Leti and Soitec detail their approaches. What is it ? In planar FD-SOI  (as opposed to the verticality of FinFETs), CMOS transistors are built into an ultra-thin layer of silicon over a Buried Oxide (BOx) (which can optionally […]

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The Moment Is Now Thumbnail

The Moment Is Now

Posted by (Hitachi) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes. Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm –  and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them. The four most significant reasons to change […]

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Low Power Analog CMOS for Cardiac Pacemakers: Design Optimization in Bulk and SOI Technologies Thumbnail

Low Power Analog CMOS for Cardiac Pacemakers: Design Optimization in Bulk and SOI Technologies

Posted by (Instituto de Ingenieria Eléctrica) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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“ Battery-operated, implantable medical devices such as pacemakers need to minimize energy consumption in order to decrease battery (hence, implant) size and maximize the time until implant substitution is required. SOI technology, particularly FD-SOI, has several advantages for these systems in terms of analog and digital ultra-low-power operation, as well as ease of implementation of […]

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Digital implementation with SOI: go with the float Thumbnail

Digital implementation with SOI: go with the float

Posted by and (Cadence Design Systems) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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Off-the-shelf solutions eliminate SOI design-time overhead. Since the drive began to make SOI a more mainstream manufacturing process there has been concern over the cost. These considerations have overshadowed the benefits that the floating body of the SOI process brings, which includes better chip performance per watt, smaller die size, and better scalability at smaller […]

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Implementing the 45nm SOI ARM11 Thumbnail

Implementing the 45nm SOI ARM11

Posted by (ARM) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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The mobile app chip’s 40% power saving was achieved without any major rework in design methodology. At the IEEE SOI Conference, ARM announced the results from a 45nm SOI test chip. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations. The goal was […]

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High volume, high yield production Thumbnail

High volume, high yield production

Posted by (KLA Tencor) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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At the 45nm node, substrate quality and uniformity are more critical than ever before to ensuring the best possible device performance. This is especially true in SOI wafers, where the substrate’s electronic structure is engineered to play an active role in enhancing carrier mobility or decreasing leakage current. Semiconductor manufacturers producing SOI-based devices utilize the […]

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Increased expectations, drastic reductions Thumbnail

Increased expectations, drastic reductions

Posted by (UC Louvain) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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Ultra-low-power design has long been confined to watches, RFID or biomedical niches. But new horizons are opening with the increasing expectations for mobile and ubiquitous devices, and with scaling enabling system-on-chips to meet lower power targets while maintaining performance.

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Understanding SRAM sense amps in SOI design Thumbnail

Understanding SRAM sense amps in SOI design

Posted by (IBM) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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As the SOI circuit switches, the body voltages of the switching transistors will change from their previous steady state condition. This is called the history effect. This is one of the most interesting circuit design issues in SOI but it is also a benefit of SOI that contributes to the SOI performance advantage over bulk […]

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SOI’s seven ESD design advantages Thumbnail

SOI’s seven ESD design advantages

Posted by (IEEE) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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SOI technology has some natural advantages in electrostatic discharge (ESD) design. At first glance, many engineers believe that it is a disadvantage to provide ESD design on SOI compared to bulk silicon technology. But, after working with SOI , there are many advantages. 1 – A first advantage is elimination of parasitic elements that can […]

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IBM & SOI: Delivering on Customer Priorities Thumbnail

IBM & SOI: Delivering on Customer Priorities

Posted by (IBM) on July 30, 2009
In ASN #13, Design & Manufacturing, In & Around Our Industry
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How IBM’s Cu-45HP ASIC leverages SOI for an overall lowering of power. Initiatives for a smarter and greener planet are creating ubiquitous demand for higher intelligence, integration and performance at the lowest possible power. New regulations, such as Energy Star, are being contemplated for many industries. Application and system requirements are prompting a dramatic shift […]

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