STMicroelectronics sees its flavor of planar FD-SOI as an excellent response to the complex needs of mobile multimedia chips. The multi-functional system-on-chips (SOC) needed at the heart of the next generations of wireless, high-performance, low-power multimedia devices have very different needs than the mono-functional processors of the past. Traditionally, the trade-off for computers and servers …

Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of …

EVG’s new wafer bonding system is a fully automated tool for production-level fabrication of 450mm SOI wafers. Transitioning to larger wafers heightens the need for process uniformity.  Wafer bonding is no exception, as process parameters must be applied with a high degree of both precision and uniformity.  This requirement will become particularly critical within the …

At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights. The roadmap for FD-SOI architectures requires SOI wafer structures with ultra-thin top silicon and ultra-thin insulating BOX (Xtreme SOI TM). Using our industry-standard Smart CutTM technology, Soitec is ramping these wafers in production …

Deeply scaled PD- and FD-SOI require new approaches to ESD protection.  Recent work from Stanford and GlobalFoundries on gate controlled FEDs shows great promise. Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits mainly by reducing MOSFET oxide and junction breakdown voltage, diode current shunting capability, and by increasing the interconnect resistivity. …

Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more. Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production …

A technological tour-de-force, Soitec’s wafers for FD SOI meet all the requirements At the 20 nm node, short channel effects and random dopant fluctuations (RDF) are the major hurdles facing the CMOS industry. An extremely attractive solution is the planar, ultra-thin body Fully-Depleted (FD) SOI transistor. These devices are built on an ultra-thin SOI substrate, …

ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models. SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each …

ST looks at a hybrid FD-SOI/bulk approach to SOCs for multimedia. The heterogeneous nature of System-on-Chip (SOC) design for the next generations of wireless, high-performance, low-power multimedia applications makes it a complex balancing act. Our research indicates that a hybrid FD-SOI/Bulk, high-k/metal-gate platform is an excellent candidate for such applications, most probably around the 22nm …

IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why. ETSOI transistors are thin-channel planar devices. Halo implantation is used to control electrostatics in conventional transistors. Although the halo controls the short channel effects, it also causes large random doping fluctuations and increases junction …