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Archive of STMicroelectronics

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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ST: FD-SOI for Competitive SOCs at 28nm and Beyond Thumbnail

ST: FD-SOI for Competitive SOCs at 28nm and Beyond

Posted by (STMicroelectronics) on November 18, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics sees its flavor of planar FD-SOI as an excellent response to the complex needs of mobile multimedia chips. The multi-functional system-on-chips (SOC) needed at the heart of the next generations of wireless, high-performance, low-power multimedia devices have very different needs than the mono-functional processors of the past. Traditionally, the trade-off for computers and servers […]

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Smart power saves power Thumbnail

Smart power saves power

Posted by (STMicroelectronics) on April 8, 2011
In ASN #17, End-User Apps, Power, SOI In Action
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ST’s newest SOI-based smart power technology delivers big reductions in power consumption in medical equipment, hybrid-electric-vehicle chargers and more. There is an urgent need for semiconductor technologies that can drastically reduce electrical energy consumption in consumer and industrial appliances. At STMicroelectronics, we have developed new SOI-based smart power technology that will make a significant difference […]

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Conquering Convergence Thumbnail

Conquering Convergence

Posted by and (STMicroelectronics) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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ST looks at a hybrid FD-SOI/bulk approach to SOCs for multimedia. The heterogeneous nature of System-on-Chip (SOC) design for the next generations of wireless, high-performance, low-power multimedia applications makes it a complex balancing act. Our research indicates that a hybrid FD-SOI/Bulk, high-k/metal-gate platform is an excellent candidate for such applications, most probably around the 22nm […]

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Closing the Rectifier Gap Thumbnail

Closing the Rectifier Gap

Posted by (STMicroelectronics) on December 3, 2008
In Advanced Substrate Corners, ASN #11, III-V
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The G2REC project leader explains the role GaN can play in solving a major energy efficiency challenge. Under the aegis of the €30 million European G2REC (Grand Gap Rectifier) project, Jean-Baptiste Quoirin of STMicroelectronics, is leading a consortium of companies and labs tackling the problem of rectifiers for things like computer server power supplies and […]

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Smaller Pixels, Brighter Pictures Thumbnail

Smaller Pixels, Brighter Pictures

Posted by (STMicroelectronics) on July 16, 2008
In Advanced Substrate Corners, ASN #10, Imaging
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ST’s 3-megapixel back-illuminated image sensor for digital cameras leverages SOI, direct wafer-level bonding and thinning technologies, improving 1.45 x 1.45 µm² pixel quantum efficiency over 60%. To meet consumer demand for higher-quality digital cameras embedded in a widening array of mobile devices, designers need image sensors with very small pixels (higher resolution, smaller, cheaper and […]

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The Promise of High Resistivity SOI for Wireless Communications Systems Thumbnail

The Promise of High Resistivity SOI for Wireless Communications Systems

Posted by (STMicroelectronics) on October 31, 2007
In ASN #8, Design & Manufacturing, In & Around Our Industry
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ST reports on highly integrated SRAM and RF on 300mm wafers. Yield matches bulk with improved FOM. Wireless communications systems may soon replace personal computers as a key driver of volume manufacturing. A full CMOS 65nm Partially Depleted Low Power (LP) SOI technology has been developed at STMicroelectronics on high resistivity (HR) (› 1kOhm-cm) 300mm […]

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Ultra-Thin Body & Box (UTB²) SOI Thumbnail

Ultra-Thin Body & Box (UTB²) SOI

Posted by (STMicroelectronics) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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As we approach the end of the roadmap, single gate FD SOI devices with ultra-thin BOX could pre-empt the need for double gate devices. It is well known that UTB (Ultra Thin Body) devices present improved electrostatic integrity. We were, however, among the first to report [1] on the importance of the BOX thickness with […]

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