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Archive of Soitec

SOITEC and UCL boost the RF performance of SOI substrates Thumbnail

SOITEC and UCL boost the RF performance of SOI substrates

Posted by and (Soitec) on December 4, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, Professor's Perspective, R&D/Labnews
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Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of […]

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Which wafers for energy-efficient, fully-depleted transistor technologies? Thumbnail

Which wafers for energy-efficient, fully-depleted transistor technologies?

Posted by (Soitec) on November 21, 2012
In ASN #20, Design & Manufacturing, In & Around Our Industry
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To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher […]

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET Thumbnail

Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

Posted by (Soitec) on April 20, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of […]

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FD-SOI: The Substrates Are Ready Thumbnail

FD-SOI: The Substrates Are Ready

Posted by (Soitec) on May 25, 2011
In ASN #17, Design & Manufacturing, In & Around Our Industry, Power
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At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights. The roadmap for FD-SOI architectures requires SOI wafer structures with ultra-thin top silicon and ultra-thin insulating BOX (Xtreme SOI TM). Using our industry-standard Smart CutTM technology, Soitec is ramping these wafers in production […]

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What Smart Stacking™ can do for you Thumbnail

What Smart Stacking™ can do for you

Posted by (Soitec) on April 22, 2011
In ASN #17, Design & Manufacturing, Imaging, In & Around Our Industry, MEMS
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Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more. Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production […]

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Wafers for Fully Depleted SOI Devices: Ready for Volume Thumbnail

Wafers for Fully Depleted SOI Devices: Ready for Volume

Posted by (Soitec) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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A technological tour-de-force, Soitec’s wafers for FD SOI meet all the requirements At the 20 nm node, short channel effects and random dopant fluctuations (RDF) are the major hurdles facing the CMOS industry. An extremely attractive solution is the planar, ultra-thin body Fully-Depleted (FD) SOI transistor. These devices are built on an ultra-thin SOI substrate, […]

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Using FD-SOI to Design Competitive Chips Thumbnail

Using FD-SOI to Design Competitive Chips

Posted by (Soitec) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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FD-SOI solves challenges without complicating design and manufacturing. Designing a successful consumer-type IC requires a balanced combination of: packing in more differentiating features, reaching good performance with low power, keeping final application costs competitive, and respecting time-to-market. Figure 1 illustrates how just a few key features intrinsic to FD-SOI translate into advantages that serve those […]

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Driving SOI Cost Reductions Thumbnail

Driving SOI Cost Reductions

Posted by (Soitec) on December 4, 2009
In ASN #14, News & Viewpoints, SOI In Action
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The SOI cost structure is on target for penetrating new markets – especially the all-important mobile markets. Volume customers can anticipate 300mm SOI wafer prices in the $500 range. As the leading SOI wafer manufacturer, Soitec has been driving optimization of its Smart Cut™ manufacturing technology for increased efficiency and continuously improving yields.

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SOI & the greening of electronics Thumbnail

SOI & the greening of electronics

Posted by (Soitec) on July 30, 2009
In ASN #13, Special supplement: SOI Industry Consortium
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The SOI Industry Consortium has a major role to play promoting the power-saving benefits of SOI. The SOI Industry Consortium has now launched the “SOI: Simply Greener” campaign.  Over the next few months, we’ll be reaching out to the industry and the press with this message.  But for our members, “green” is much more than […]

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