STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology …

Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of …

At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights. The roadmap for FD-SOI architectures requires SOI wafer structures with ultra-thin top silicon and ultra-thin insulating BOX (Xtreme SOI TM). Using our industry-standard Smart CutTM technology, Soitec is ramping these wafers in production …

Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more. Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production …

A technological tour-de-force, Soitec’s wafers for FD SOI meet all the requirements At the 20 nm node, short channel effects and random dopant fluctuations (RDF) are the major hurdles facing the CMOS industry. An extremely attractive solution is the planar, ultra-thin body Fully-Depleted (FD) SOI transistor. These devices are built on an ultra-thin SOI substrate, …

FD-SOI solves challenges without complicating design and manufacturing. Designing a successful consumer-type IC requires a balanced combination of: packing in more differentiating features, reaching good performance with low power, keeping final application costs competitive, and respecting time-to-market. Figure 1 illustrates how just a few key features intrinsic to FD-SOI translate into advantages that serve those …

The SOI cost structure is on target for penetrating new markets – especially the all-important mobile markets. Volume customers can anticipate 300mm SOI wafer prices in the $500 range. As the leading SOI wafer manufacturer, Soitec has been driving optimization of its Smart Cut™ manufacturing technology for increased efficiency and continuously improving yields.

The SOI Industry Consortium has a major role to play promoting the power-saving benefits of SOI. The SOI Industry Consortium has now launched the “SOI: Simply Greener” campaign.  Over the next few months, we’ll be reaching out to the industry and the press with this message.  But for our members, “green” is much more than …

SOI and other engineered substrates drive power efficiency through the value chain.

Transferring the entire layer of circuits from a processed wafer to the best substrate for the application is now available for custom manufacturing or technology transfer. The Soitec Group recently announced that Smart Stacking™, our circuit stacking technology, is ready for both manufacturing and technology transfer.