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IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI Thumbnail

IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI

Posted by (IBM) on April 18, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
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Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, […]

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IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value Thumbnail

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value

Posted by (IBM) on November 30, 2012
In Advanced Substrate Corners, ASN #20, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
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FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, […]

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ETSOI Substrates: What We Needi Thumbnail

ETSOI Substrates: What We Needi

Posted by (IBM) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why. ETSOI transistors are thin-channel planar devices. Halo implantation is used to control electrostatics in conventional transistors. Although the halo controls the short channel effects, it also causes large random doping fluctuations and increases junction […]

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Understanding SRAM sense amps in SOI design Thumbnail

Understanding SRAM sense amps in SOI design

Posted by (IBM) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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As the SOI circuit switches, the body voltages of the switching transistors will change from their previous steady state condition. This is called the history effect. This is one of the most interesting circuit design issues in SOI but it is also a benefit of SOI that contributes to the SOI performance advantage over bulk […]

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IBM & SOI: Delivering on Customer Priorities Thumbnail

IBM & SOI: Delivering on Customer Priorities

Posted by (IBM) on July 30, 2009
In ASN #13, Design & Manufacturing, In & Around Our Industry
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How IBM’s Cu-45HP ASIC leverages SOI for an overall lowering of power. Initiatives for a smarter and greener planet are creating ubiquitous demand for higher intelligence, integration and performance at the lowest possible power. New regulations, such as Energy Star, are being contemplated for many industries. Application and system requirements are prompting a dramatic shift […]

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Analog Circuit Design in SOI Thumbnail

Analog Circuit Design in SOI

Posted by (IBM) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
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SOI provides key advantages for analog designers. Here’s how and why. Many technical studies have shown that SOI CMOS technology offers substantial digital circuit performance improvements over bulk CMOS at the same lithography node. As more CMOS fabs transition to SOI to enable these gains, analog circuit designers are faced with the task of accommodating […]

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The Path Towards CMOS-Photonics Monolithic Integration Thumbnail

The Path Towards CMOS-Photonics Monolithic Integration

Posted by (IBM) on October 31, 2007
In Advanced Substrate Corners, ASN #8, Photonics
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IBM researchers have made strategic advances in key elements needed to achieve on-chip optical networks. The current trend in the microelectronics industry is to increase the parallelism in computation by multi-threading, by building large-scale multichip systems and, more recently, by increasing the number of cores on a single chip. With such an increase of parallelization […]

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RF All-In-One

Posted by (IBM) on October 31, 2007
In ASN #8, Design & Manufacturing, In & Around Our Industry
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IBM’s new CMOS 7RF SOI technology offers significant cost advantages to designers of mobile handsets. For mobile phones, laptops and other portable communication devices to reach a broad user base in emerging markets, designers need affordable, power-efficient and high-performance solutions that will further reduce the complexity of components. To that end, IBM has recently introduced […]

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Embedded Memories in SOI Thumbnail

Embedded Memories in SOI

Posted by (IBM) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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Embedded DRAM on SOI is set to proliferate at the 45nm node. Embedded memory now occupies close to 75% of the total chip area. Until a few years ago, this memory was exclusively SRAM, but more recently the industry has seen a significant transition to embedded DRAMs (eDRAMs).

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IBM Nanoscale Probe Storage System Leverages SOI in New Frontiers Thumbnail

IBM Nanoscale Probe Storage System Leverages SOI in New Frontiers

Posted by (IBM) on July 11, 2006
In ASN #5, In & Around Our Industry, MEMS
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An IBM-Zurich team including Nobel laureates has extended the Atomic Force Microscopy (AFM) concept to data storage. IBM group manager and probe storage team member Michel Despont explains. While today’s magnetic data storage techniques are reaching some impressive levels, at some point in the not too distant future they will hit the physical limits of […]

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