Archive of CEA-Leti

Leti: Adding Strain to FD-SOI for 20nm and Beyond Thumbnail

Leti: Adding Strain to FD-SOI for 20nm and Beyond

Posted by and (CEA-Leti) on April 30, 2012
In Advanced Substrate Corners, ASN #19, R&D/Labnews
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Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated […]

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Model Behavior Thumbnail

Model Behavior

Posted by (CEA-Leti) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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Leti has compact models ready for FD-SOI SPICE simulations. A critical link in the move to FD-SOI is the availability of robust compact models. Compact models of transistors and other elementary devices are used to predict the behavior of a design.  As such, they are embedded in simulations like SPICE that designers run before actual […]

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In the Lab Thumbnail

In the Lab

Posted by (CEA-Leti) on July 26, 2010
In ASN #15, End-User Apps, SOI In Action
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“Currently at Leti, we use SOI in health-related research more for dimensional requirements than intrinsic electrical properties. For example, reproducibility in the cavity size (z-axis) is of prime importance for dilution and biological protocols. Some specific studies in capacitive detection, however, do leverage the electrical advantages of SOI.”

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Sources Discovered

Posted by (CEA-Leti) on May 27, 2009
In Advanced Substrate Corners, ASN #12, Conferences
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Leti, Soitec and ST have discovered the sources of threshold voltage variation in undoped, ultrathin FD-SOI architectures. At the most recent IEDM conference, researchers from Leti, Soitec and STMicroelectronics presented a paper entitled, “High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding” (O. Weber et al, IEDM 2008).

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The Promise of FD-SOI for Low Power Applications Thumbnail

The Promise of FD-SOI for Low Power Applications

Posted by (CEA-Leti) on May 14, 2008
In Advanced Substrate Corners, ASN #9, R&D/Labnews
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CEA-LETI reports on FD-SOI technology developed for the 32nm node and beyond. A Fully Depleted SOI CMOS technology has been developed at CEA-LETI for Low Power applications at 32nm nodes and below. For years, fully depleted devices have been considered as electrostatic boosters due the fact that they benefit from smaller short channel effects than […]

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On the Smart Cut™ Frontier

Posted by (CEA-Leti) on July 11, 2005
In ASN #2, News & Viewpoints, SOI In Action
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The inventor of Smart Cut technology, Dr. Bruel reflects on its impact for the industry. I knew a time when it was very common to encounter people who didn’t believe in the future of SOI technology, when people thought that only bulk silicon technologies would solve microelectronics’ new challenges.

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