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SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
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Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

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IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers Thumbnail

IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers

Posted by (ARM) on May 17, 2013
In Advanced Substrate Corners, Conferences
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IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference Hyatt Regency Monterey Hotel and Spa, Monterey, California October 7th thru 10th, 2013 In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS […]

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Bulk logic designs for mobile apps port directly to FD-SOI Thumbnail

Bulk logic designs for mobile apps port directly to FD-SOI

Posted by (ARM) on November 4, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of […]

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Right Timing Thumbnail

Right Timing

Posted by (ARM) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models. SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each […]

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Implementing the 45nm SOI ARM11 Thumbnail

Implementing the 45nm SOI ARM11

Posted by (ARM) on December 4, 2009
In ASN #14, Design & Manufacturing, In & Around Our Industry
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The mobile app chip’s 40% power saving was achieved without any major rework in design methodology. At the IEEE SOI Conference, ARM announced the results from a 45nm SOI test chip. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations. The goal was […]

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Energy-Efficient SoC Design Can Make A Difference Thumbnail

Energy-Efficient SoC Design Can Make A Difference

Posted by (ARM) on July 30, 2009
In ASN #13, Design & Manufacturing, In & Around Our Industry
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ARM now offers a combination of low-power processors, SOI libraries and power management IP. It is often the simple actions that make the largest impact when it comes to conserving our natural resources and limiting the negative impact of human interaction on our planet. Conserving our natural and manufactured energy resources is certainly at the […]

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2008: ARM Lays the SOI Foundation Thumbnail

2008: ARM Lays the SOI Foundation

Posted by (ARM) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
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This fall, ARM will be rolling out key physical IP libraries, opening the door to broad SOI adoption. As the leading processor IP company, ARM is collaborating with industry partners to facilitate the adoption of SOI CMOS technology. ARM’s optimized SOI Physical IP libraries target development of high-speed and low dynamicpower SoC designs in 45nm […]

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SOI for ASICs: Right Into the Flow Thumbnail

SOI for ASICs: Right Into the Flow

Posted by (ARM) on May 11, 2007
In News & Viewpoints, SOI In Action
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Here’s why ARM, the industry’s leading provider of intellectual property for processor, peripheral and SoC design, sees SOI technology as a powerful tool in the quest for optimized performance and power consumption. Silicon-On-Insulator (SOI) technology offers designers an opportunity for product differentiation and value creation. Adopting well-designed SOI physical IP products gives ASIC designers additional […]

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