ASN

Archive of R&D/Labnews

NIST Nanowire Transistors on SOI Thumbnail

NIST Nanowire Transistors on SOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
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New design simplifies processing and on/off switching Using SOI as the substrate, researchers at the National Institute of Standards and Technology (NIST) have overcome some of the main challenges to making silicon nanowire devices. As noted in the journal “Nanotechnology” (June, 2005), the NIST design uses a simplified type of contact between the nanowire channel […]

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MIRAI-ASET Working on SGOI and GeOI Thumbnail

MIRAI-ASET Working on SGOI and GeOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
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3,1 times greater hole-mobility observed in ultra-thin GeOI   MIRAI-ASET, a government-sponsored Japanese research consortium, has been working on SGOI (SiGe on Insulator) and GeOI (Germanium on Insulator) for high-performance CMOS. Recent findings were reported at the last International Conference on Solid State Devices and Materials (S.Nakaharai et al.; SSDM 2005, pp.868-869, Kobe, Japan). They […]

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More and More Strain

Posted by (Soitec) on December 7, 2005
In Advanced Substrate Corners, ASN #3, R&D/Labnews
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Dr. Yoshimi reviews some recent approaches to strained SOI implementation Implementing strain into the channel of MOSFETs has become mainstream technology for high-performance CMOS-FETs. Process induced uniaxial stress is being used today to boost carrier mobilities of sub-µm devices and thus improve IC performance.

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MEDEA+ 2T101: sSOI for High-Performance ICs

Posted on July 11, 2005
In ASN #2, In & Around Our Industry, R&D/Labnews
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The objective is to provide an industrial source of large diameter strained SOI wafers within 3 years. A “Phase 2” MEDEA+ project, 2T101, known as SILONIS is currently ramping up. The project, which is lead by Soitec, involves 15 partners, including suppliers and IC makers active in four different European countries.

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OPTIMUM

Posted on July 11, 2005
In ASN #2, In & Around Our Industry, R&D/Labnews
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Financing approved for new III-V program The first phase of OPTIMUM, a new III-V research project lead by Thales Communications France (TCF) and partners UMS, OMMIC and Picogiga International, has recently been approved and financed. There are four sub-sections within the pro-ject. The first focuses on innovative III-V materials and technologies, in particular the optimization […]

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Substrate strategies for high-performance and low-power applications at 45 nm

Posted by (Soitec) on July 11, 2005
In Advanced Substrate Corners, ASN #2, R&D/Labnews
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Two distinct technical strategies for advanced substrates will mark the 45nm node. One will be focused on high performance, the other driven by system-on-chip (SOC) applications, including low power, portable RF applications. The high performance path will drive the most advanced substrates and material innovations. Engineered substrate solutions include ultra-thin (UT) SOI, mobility enhancing substrates […]

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MEDEA+ T206: CMOS SOI for low power logic and RF wireless (CMOSSOI)

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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Ongoing since 2002, the MEDEA+ T206 CMOS SOI project is scheduled to finish up this September. The objective is: “…to evaluate, design and manufacture a family of CMOS silicon-on- insulator (SOI) circuits for low-power portable, radio frequency (RF) wireless and high-speed applications to compete with more expensive CMOS and bipolar CMOS (BiCMOS) devices.” The program, […]

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ATDF MuGFET Development Program

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar […]

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Soitec Characterization Lab

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electrical and physico-chemical tests such as Psi-Mos, Hg-fet, CV, Box integrity, BMD and SECCO on SOI, sSOI and new materials. R&D researchers in the lab are developing new characterization techniques for future needs. The lab is audited regularly by customers, […]

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EUROSOI

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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A preliminary public version of the “EUROSOI State of the Art Report” is now available at www.eurosoi.org. It compiles the contributions of more than 150 researchers/experts from 14 European countries active in SOI technology, devices and systems. A listing of current European and national SOI projects is also available on the site •

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