ASN

Archive of R&D/Labnews

Substrate strategies for high-performance and low-power applications at 45 nm

Posted by Carlos MAZURE (Soitec) on July 11, 2005
In Advanced Substrate Corners, ASN #2, R&D/Labnews
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Two distinct technical strategies for advanced substrates will mark the 45nm node. One will be focused on high performance, the other driven by system-on-chip (SOC) applications, including low power, portable RF applications. The high performance path will drive the most advanced substrates and material innovations. Engineered substrate solutions include ultra-thin (UT) SOI, mobility enhancing substrates …

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MEDEA+ T206: CMOS SOI for low power logic and RF wireless (CMOSSOI)

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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Ongoing since 2002, the MEDEA+ T206 CMOS SOI project is scheduled to finish up this September. The objective is: “…to evaluate, design and manufacture a family of CMOS silicon-on- insulator (SOI) circuits for low-power portable, radio frequency (RF) wireless and high-speed applications to compete with more expensive CMOS and bipolar CMOS (BiCMOS) devices.” The program, …

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ATDF MuGFET Development Program

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar …

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Soitec Characterization Lab

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electrical and physico-chemical tests such as Psi-Mos, Hg-fet, CV, Box integrity, BMD and SECCO on SOI, sSOI and new materials. R&D researchers in the lab are developing new characterization techniques for future needs. The lab is audited regularly by customers, …

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EUROSOI

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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A preliminary public version of the “EUROSOI State of the Art Report” is now available at www.eurosoi.org. It compiles the contributions of more than 150 researchers/experts from 14 European countries active in SOI technology, devices and systems. A listing of current European and national SOI projects is also available on the site •

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45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI Thumbnail

45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI

Posted on April 18, 2005
In Advanced Substrate Corners, ASN #1, R&D/Labnews
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The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a Soitec™ UNIBOND™ SOI wafer (88nm Si thickness / 145nm BOx thickness). The reticle was designed to print fins down to 30nm fin width and it incorporated various capacitors, NMOS/PMOS/CMOS transistors …

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