ASN

Archive of R&D/Labnews

High-k and Metal Gates Pave the Way to Further Innovation Thumbnail

High-k and Metal Gates Pave the Way to Further Innovation

Posted by (Soitec) on May 11, 2007
In Advanced Substrate Corners, ASN #7, R&D/Labnews
Tagged with , , , ,

Here’s why HK+MG+SOI promises to be a winning combination. Seen as a necessary innovation to assure the IC scaling path, high-k gate dielectrics combined with metal gates have been in development for more than a decade. Recent announcements by IC technology leaders highlight the transition from R&D to early manufacturing for high-k and metal gate […]

Continue ReadingLeave a Comment
UT BOX SOI: Engineering for Future Low-Power Applications Thumbnail

UT BOX SOI: Engineering for Future Low-Power Applications

Posted by (Soitec) on December 6, 2006
In Advanced Substrate Corners, ASN #6, R&D/Labnews
Tagged with , , ,

Ultra-thin buried oxide may solve some key design challenges at 32nm. Leading-edge microprocessors built on SOI have maximized performance while respecting the power budget by decoupling the Si surface from the substrate with a 150nm-thick buried oxide (BOX). However, moving towards low-power, high- or mid-performance CMOS applications, an increased coupling between the top layer of […]

Continue ReadingLeave a Comment
Strained Silicon-On-Insulator (sSOI) Becomes an Industrial Reality Thumbnail

Strained Silicon-On-Insulator (sSOI) Becomes an Industrial Reality

Posted by (Soitec) on July 11, 2006
In Advanced Substrate Corners, ASN #5, R&D/Labnews

After several years of rigorous R&D work in close partnership with suppliers and customers alike, Soitec’s sSOI wafers are now ready for industrialization. The benefits of strained silicon as an amplifier of carrier mobility, current drive and, as a result, device performance are well documented in literature and highlighted by Dr. Nguyen of Freescale in […]

Continue ReadingLeave a Comment
EuroSOI Gears Up for Next Programme Thumbnail

EuroSOI Gears Up for Next Programme

Posted on April 6, 2006
In ASN #4, In & Around Our Industry, R&D/Labnews
Tagged with

Network successfully federating research collaboration. Now entering its third year, the EuroSOI Thematic Network on Silicon on Insulator Technology, Devices and Circuits is delivering on its charter to “federate the existing research network on SOI topics.” It is under the aegis of the European Commission’s research activities, which are structured around consecutive, four-year Framework Programmes […]

Continue ReadingLeave a Comment
Medea+ sSOI Partners Now Public Thumbnail

Medea+ sSOI Partners Now Public

Posted on April 6, 2006
In ASN #4, In & Around Our Industry, R&D/Labnews
Tagged with ,

Program includes AMD, Freescale, Infineon, Philips and ST. The list of partners in the Medea+ Strained Silicon-On-Insulator Substrates for High Performance ICs program, known as SilOnIS, has now been made public. Among the corporate partners are AMD, ASM, Freescale, Infineon, Philips, Siltronic and ST, among others. Lead by Soitec, the project’s stated goal is to […]

Continue ReadingLeave a Comment

Strained Silicon on Insulator: the Wafer Solution for Low-Power and High-Performance Devices

Posted by (Soitec) on April 6, 2006
In Advanced Substrate Corners, ASN #4, R&D/Labnews
Tagged with , , , ,

sSOI is on-track for high-volume manufacturing at the 45nm node. The end of conventional scaling is a topic that has generated discussion and controversy within the semiconductor community. The fact is that IC density increase through device geometry shrinking no longer results in an IC performance increase if the scaling is not coupled to the […]

Continue ReadingLeave a Comment
NIST Nanowire Transistors on SOI Thumbnail

NIST Nanowire Transistors on SOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
Tagged with ,

New design simplifies processing and on/off switching Using SOI as the substrate, researchers at the National Institute of Standards and Technology (NIST) have overcome some of the main challenges to making silicon nanowire devices. As noted in the journal “Nanotechnology” (June, 2005), the NIST design uses a simplified type of contact between the nanowire channel […]

Continue ReadingLeave a Comment
MIRAI-ASET Working on SGOI and GeOI Thumbnail

MIRAI-ASET Working on SGOI and GeOI

Posted on December 7, 2005
In ASN #3, In & Around Our Industry, R&D/Labnews
Tagged with ,

3,1 times greater hole-mobility observed in ultra-thin GeOI   MIRAI-ASET, a government-sponsored Japanese research consortium, has been working on SGOI (SiGe on Insulator) and GeOI (Germanium on Insulator) for high-performance CMOS. Recent findings were reported at the last International Conference on Solid State Devices and Materials (S.Nakaharai et al.; SSDM 2005, pp.868-869, Kobe, Japan). They […]

Continue ReadingLeave a Comment

More and More Strain

Posted by (Soitec) on December 7, 2005
In Advanced Substrate Corners, ASN #3, R&D/Labnews
Tagged with , , , , , ,

Dr. Yoshimi reviews some recent approaches to strained SOI implementation Implementing strain into the channel of MOSFETs has become mainstream technology for high-performance CMOS-FETs. Process induced uniaxial stress is being used today to boost carrier mobilities of sub-µm devices and thus improve IC performance.

Continue ReadingLeave a Comment

MEDEA+ 2T101: sSOI for High-Performance ICs

Posted on July 11, 2005
In ASN #2, In & Around Our Industry, R&D/Labnews
Tagged with , ,

The objective is to provide an industrial source of large diameter strained SOI wafers within 3 years. A “Phase 2” MEDEA+ project, 2T101, known as SILONIS is currently ramping up. The project, which is lead by Soitec, involves 15 partners, including suppliers and IC makers active in four different European countries.

Continue ReadingLeave a Comment