Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, …

FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, …

Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated …

Leading equipment and materials suppliers have created the European 450mm Equipment and Materials Initiative – or EEMI 450, for short. The steering committee comprises two substrate manufacturers (Soitec and Siltronic), three equipment suppliers (ASML, ASM, Recif), academics (IMEC, FHG) and Intel. EEMI 450’s global counterparts are ITB-J (Interoperability Test Bed – Japan) and ISMI (International …

Project targets advanced materials for improved performance and electrical consumption. The Soitec Group, CEA-LETI and the French Agency for Industrial Innovation (AII) have teamed up on a new, €200 million materials research program dubbed the “NanoSmart” project. Nelly Kernevez, a well-known Léti researcher who recently joined Soitec, will head up the project. The European Commission …

Soitec’s core technologies are building blocks for 3D integration. At the wafer level, molecular bonding techniques and Smart Cut technology add significant value to 3D integration. A good application for these building blocks is backside illuminated image sensors (BIS), which is probably the most mature 3D technology and close to mass production. For standard front …

CEA-LETI reports on FD-SOI technology developed for the 32nm node and beyond. A Fully Depleted SOI CMOS technology has been developed at CEA-LETI for Low Power applications at 32nm nodes and below. For years, fully depleted devices have been considered as electrostatic boosters due the fact that they benefit from smaller short channel effects than …

The ITRS calls for ultra-thin body devices to enter manufacturing in just a few years. The stringent SOI substrate requirements are met with high-volume manufacturing technology. SOI technology is developing toward Ultra-Thin Body (UTB) semiconductor layers with fully depleted (FD-SOI) and Multiple Gate FETs (MuGFETs), consistent with the latest version of the ITRS. The current …

SOI-based memory reverses cache crunch and simplifies DRAM scaling, boosting performance and reducing cost. Memory today represents about 25% of the estimated $260B worldwide semiconductor market. The two dominant players are DRAM (56%) and FLASH (33%). Further, memory in the form of embedded SRAM cache is becoming the dominant area user and technology driver for …

SOI-based Smart Power Innovator Atmel leads new Medea+ program. Atmel, a leading proponent of SOI for Smart Power, is heading up a new Medea+ program called SPOT-2 (program #2T205), for Deep Sub-micron Smart-Power Technologies. The 3-year program aims to develop a new generation of Smart Power Technologies for automotive and consumer applications. More than a …