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Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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SOITEC and UCL boost the RF performance of SOI substrates Thumbnail

SOITEC and UCL boost the RF performance of SOI substrates

Posted by and (Soitec) on December 4, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, Professor's Perspective, R&D/Labnews
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Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of […]

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IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI Thumbnail

IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI

Posted by (IBM) on April 18, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
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Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, […]

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IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value Thumbnail

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value

Posted by (IBM) on November 30, 2012
In Advanced Substrate Corners, ASN #20, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
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FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, […]

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Leti: Adding Strain to FD-SOI for 20nm and Beyond Thumbnail

Leti: Adding Strain to FD-SOI for 20nm and Beyond

Posted by and (CEA-Leti) on April 30, 2012
In Advanced Substrate Corners, ASN #19, R&D/Labnews
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Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated […]

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The Next Big Thing Thumbnail

The Next Big Thing

Posted on July 26, 2010
In Advanced Substrate Corners, ASN #15, R&D/Labnews
Tagged with

Leading equipment and materials suppliers have created the European 450mm Equipment and Materials Initiative – or EEMI 450, for short. The steering committee comprises two substrate manufacturers (Soitec and Siltronic), three equipment suppliers (ASML, ASM, Recif), academics (IMEC, FHG) and Intel. EEMI 450’s global counterparts are ITB-J (Interoperability Test Bed – Japan) and ISMI (International […]

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EC Approves €200 Million NanoSmart

Posted on October 31, 2008
In ASN #8, In & Around Our Industry, R&D/Labnews
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Project targets advanced materials for improved performance and electrical consumption. The Soitec Group, CEA-LETI and the French Agency for Industrial Innovation (AII) have teamed up on a new, €200 million materials research program dubbed the “NanoSmart” project. Nelly Kernevez, a well-known Léti researcher who recently joined Soitec, will head up the project. The European Commission […]

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3D at the Wafer Level

Posted by (Soitec) on July 16, 2008
In Advanced Substrate Corners, ASN #10, R&D/Labnews
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Soitec’s core technologies are building blocks for 3D integration. At the wafer level, molecular bonding techniques and Smart Cut technology add significant value to 3D integration. A good application for these building blocks is backside illuminated image sensors (BIS), which is probably the most mature 3D technology and close to mass production. For standard front […]

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The Promise of FD-SOI for Low Power Applications Thumbnail

The Promise of FD-SOI for Low Power Applications

Posted by (CEA-Leti) on May 14, 2008
In Advanced Substrate Corners, ASN #9, R&D/Labnews
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CEA-LETI reports on FD-SOI technology developed for the 32nm node and beyond. A Fully Depleted SOI CMOS technology has been developed at CEA-LETI for Low Power applications at 32nm nodes and below. For years, fully depleted devices have been considered as electrostatic boosters due the fact that they benefit from smaller short channel effects than […]

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