SOI is at the heart of silicon photonics. Here’s an overview of past, present and future trends. The existence of Silicon Photonics owes much to serendipity. During the early years of the development of SOI wafer technology probably nobody anticipated that SOI would be a perfect medium for short distance transmission and modulation of light …

Researchers in academia have partnered with industry to increase understanding of critical issues in advanced non-classical CMOS devices. Highly scaled devices present a new range of challenges with respect to critical issues such as leakage current, short-channel effects, high-field effects, variability, reliability, noise and parasitic impact. Device structure and material innovation are the primary enablers …

Key advances in transistor research start on SOI. SOI has always been the substrate of choice to explore new silicon device concepts and structures. The full dielectric isolation of the silicon allows one to dismiss the sometimes complex junction isolation schemes used in bulk silicon. The possibility of making devices in thin silicon films has …

What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may …

A leading figure in the research world, Professor Woo and his team are taking an innovative approach to taming the power challenge.

SOI is major contender for heterogeneous applications. The advantages of SOI technology for building thin film sensors on membranes as well as three-dimensional (3D) surface micromachined sensors and actuators have been demonstrated over these last years. The flatness and robustness of the thin membrane as well as the self-assembling of out-of-plane 3D microstructures rely on …

Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure? The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has been proposed for scaling CMOS technology to sub-45nm nodes. This is because short-channel effects (manifested in increasing off-state leakage with increasing drain bias and with decreasing gate length) are well suppressed in a FD-SOI MOSFET when the …

One of the world’s leading experts, Professor Fossum explains why SOI represents a pragmatic approach to future transistor generations. Based on our recent studies of multi-gate MOSFETs (“MuGFETs”) for CMOS applications, which are mainly modeling- and simulation-based with experimental support from Freescale Semiconductor, we have suggested that nanoscale FinFETs can and should be designed pragmatically, …

Starting with SOI wafers, Professor Lagally’s team has developed strain-engineered silicon nanomembranes that could pave the way to flexible, high-speed circuits and more. SOI, beyond its well-known use in CMOS devices, provides the foundation for a new class of structures: strain engineered Si nanomembranes. These membranes offer the promise for new devices or increased performance …

The semiconductor industry has entered an exciting phase in which further performance gains (power, speed) are directly connected to materials engineering and the insertion of new materials into the heart of silicon integrated circuits. The rate at which the industry is incorporating strain engineering into production is a direct result of using strained substrate materials …