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IEEE SOI-3D-Subthreshold Conference (S3S, Oct. Sonoma, CA) Welcoming Papers til mid-May Thumbnail

IEEE SOI-3D-Subthreshold Conference (S3S, Oct. Sonoma, CA) Welcoming Papers til mid-May

Posted by on April 27, 2015
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The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 18, 2015. Last year, the second edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success targetting key topics and attracting even more participants than […]

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RF-SOI: Already in Every Smartphone, New Opps Abound in IoT (SF Workshop Part 3 of 3: IBM, ST, GF and more) Thumbnail

RF-SOI: Already in Every Smartphone, New Opps Abound in IoT (SF Workshop Part 3 of 3: IBM, ST, GF and more)

Posted by on March 11, 2015
In Conferences, Design & Manufacturing, Editor's Blog
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RF-SOI is already found in virtually every new smartphone out there, so the RF-SOI session of the recent FD-SOI/RF-SOI Workshop in San Francisco focused on long-term growth and further opportunities. In case you missed it, ASN already covered the SF Workshop’s FD-SOI presentations (Samsung, ST and the EDA houses – click here for that post) […]

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Yes, Cisco Is Doing a 28nm FD-SOI Chip! (Part 2 of 3, SF Workshop: FD-SOI Panel Discussion) Thumbnail

Yes, Cisco Is Doing a 28nm FD-SOI Chip! (Part 2 of 3, SF Workshop: FD-SOI Panel Discussion)

Posted by on March 5, 2015
In Conferences, Design & Manufacturing, Editor's Blog
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More good news: Cisco is working on a 28nm FD-SOI chip. This additional boost to FD-SOI momentum was revealed during the Panel Discussion at the recent FD-SOI/RF-SOI Workshop in San Francisco. The EETimes coverage (which also revealed that Freescale’s putting its next-gen iMX7 microprocessor on 28nm FD-SOI – you can read it here) was quickly […]

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Big Boost for FD-SOI Momentum Seen at SF Workshop  –  Part 1 of 3: The FD-SOI Presentations (ST, Samsung, EDA & Design Houses) Thumbnail

Big Boost for FD-SOI Momentum Seen at SF Workshop – Part 1 of 3: The FD-SOI Presentations (ST, Samsung, EDA & Design Houses)

Posted by on March 3, 2015
In Conferences, Design & Manufacturing, Editor's Blog
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The FD-SOI/RF-SOI Workshop in San Francisco last week was a huge success. Over 150 people from over 80 companies attended the all-day event. There were excellent presentations, animated Q&A sessions, and lots of networking going on over coffee, lunch and cocktails.  It generated excellent press (click here to see the EETimes feature) and lots of […]

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Top Silicon Valley Companies Signed Up for FD-SOI & RF-SOI Forum (27 Feb. 2015 in SF, free, registration still open) Thumbnail

Top Silicon Valley Companies Signed Up for FD-SOI & RF-SOI Forum (27 Feb. 2015 in SF, free, registration still open)

Posted by on February 23, 2015
In Conferences, Editor's Blog
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Name a top Silicon Valley company, and you’ll probably find it on the attendance list of the upcoming FD-SOI & RF-SOI Forum in San Francisco. At the time of this posting, people from over 65 companies are among the hundreds who’ve signed up for this free, all-day event. If you haven’t yet, you can still […]

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SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage) Thumbnail

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

Posted by on January 12, 2015
In Conferences, Paperlinks, R&D/Labnews
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Important SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. Here in Part 3, we’ll […]

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SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage) Thumbnail

SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage)

Posted by on January 9, 2015
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Beyond FD-SOI and FinFETs, important SOI-based developments in advanced device architectures including nanowires (NW), gate all around (GAA) and other FET structures shared the spotlight at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. Here in Part 2 of […]

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10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage) Thumbnail

10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage)

Posted by on December 31, 2014
In Conferences, Paperlinks, R&D/Labnews
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FD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we […]

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Successful RF-SOI 2014 International Symposium Held in Shanghai Thumbnail

Successful RF-SOI 2014 International Symposium Held in Shanghai

Posted by and on December 5, 2014
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A very successful international workshop on RF-SOI was held in Shanghai earlier this fall.  Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications.Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem and […]

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SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications Thumbnail

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

Posted by and on November 3, 2014
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ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. […]

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