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Archive of Advanced Substrate Corners

Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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FD-SOI Opportunities in China Thumbnail

FD-SOI Opportunities in China

Posted by on February 5, 2014
In Design & Manufacturing, News & Viewpoints, Professor's Perspective
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Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS) The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment. The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in […]

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IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers Thumbnail

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

Posted by on December 19, 2013
In Conferences, Editor's Blog, Paperlinks
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SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices. Brief summaries, culled […]

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The FD-SOI Papers at IEDM ’13 Thumbnail

The FD-SOI Papers at IEDM ’13

Posted by on December 16, 2013
In Conferences, Editor's Blog, Paperlinks
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FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI […]

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SOITEC and UCL boost the RF performance of SOI substrates Thumbnail

SOITEC and UCL boost the RF performance of SOI substrates

Posted by and (Soitec) on December 4, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, Professor's Perspective, R&D/Labnews
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Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of […]

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The IEEE S3S Conference Delivered Impressive Technical Content Thumbnail

The IEEE S3S Conference Delivered Impressive Technical Content

Posted by on November 18, 2013
In Conferences
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The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

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Foundry, Experts at Shanghai FD-SOI Workshop Indicate Major Opportunities in China Thumbnail

Foundry, Experts at Shanghai FD-SOI Workshop Indicate Major Opportunities in China

Posted by on November 8, 2013
In Advanced Substrate Corners, Conferences, News & Viewpoints, SOI In Action
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Aiming to promote the benefits of SOI technology and reduce the barriers to market adoption, the SOI Industry Consortium (a group of leading companies with the mission of accelerating SOI innovation into broad markets), SIMIT (Shanghai Institute of Microsystem and Information Technology), CAS (a pioneer of SOI technology in China), and VeriSilicon Holdings Co., Ltd. […]

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SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
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Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

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Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers Thumbnail

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Posted by on June 12, 2013
In Advanced Substrate Corners, Conferences, Editor's Blog, Paperlinks
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Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions. Here’s a […]

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