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Successful RF-SOI 2014 International Symposium Held in Shanghai Thumbnail

Successful RF-SOI 2014 International Symposium Held in Shanghai

Posted by and on December 5, 2014
In Conferences
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A very successful international workshop on RF-SOI was held in Shanghai earlier this fall.  Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications. Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem […]

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SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications Thumbnail

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

Posted by and on November 3, 2014
In Conferences
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ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. […]

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Is China Interested in FD-SOI? You bet. Thumbnail

Is China Interested in FD-SOI? You bet.

Posted by on October 28, 2014
In Conferences, Editor's Blog, In & Around Our Industry
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At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. The event was sponsored by the SOI Consortium, the Shanghai Institute of Microsystem and Information Technology / Chinese Academy of Sciences (SIMIT/CAS), and VeriSilicon. By all accounts it was a great success. Speakers included experts […]

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FD-SOI Front and Center at Very Successful Semicon Europa Thumbnail

FD-SOI Front and Center at Very Successful Semicon Europa

Posted by on October 17, 2014
In Conferences, Editor's Blog
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Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014). This was Semicon Europa’s first time in Grenoble, the heart […]

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Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more Thumbnail

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

Posted by on September 26, 2014
In Conferences, Editor's Blog
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  For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry. And Grenoble can fairly be considered the epicenter of […]

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Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct) Thumbnail

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

Posted by on September 17, 2014
In Conferences, R&D/Labnews
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(For best rates, register by September 18th.) The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco. Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S […]

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The SOI Papers at VLSI ’14 (Part 2): Thumbnail

The SOI Papers at VLSI ’14 (Part 2):

Posted by on July 17, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.) This […]

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The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs Thumbnail

The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

Posted by on July 11, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four […]

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2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May Thumbnail

2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May

Posted by on May 22, 2014
In Conferences
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IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference 6-9 October 2014 Westin San Francisco Airport, Millbrae, CA The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).   Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE […]

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Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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