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Archive of Advanced Substrate Corners

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more Thumbnail

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

Posted by on September 26, 2014
In Conferences, Editor's Blog
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  For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry. And Grenoble can fairly be considered the epicenter of […]

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Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct) Thumbnail

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

Posted by on September 17, 2014
In Conferences, R&D/Labnews
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(For best rates, register by September 18th.) The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco. Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S […]

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The SOI Papers at VLSI ’14 (Part 2): Thumbnail

The SOI Papers at VLSI ’14 (Part 2):

Posted by on July 17, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.) This […]

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The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs Thumbnail

The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

Posted by on July 11, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four […]

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2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May Thumbnail

2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May

Posted by on May 22, 2014
In Conferences
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , ,

IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference 6-9 October 2014 Westin San Francisco Airport, Millbrae, CA The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).   Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE […]

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Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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FD-SOI Opportunities in China Thumbnail

FD-SOI Opportunities in China

Posted by on February 5, 2014
In Design & Manufacturing, News & Viewpoints, Professor's Perspective
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Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS) The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment. The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in […]

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IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers Thumbnail

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

Posted by on December 19, 2013
In Conferences, Editor's Blog, Paperlinks
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SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices. Brief summaries, culled […]

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The FD-SOI Papers at IEDM ’13 Thumbnail

The FD-SOI Papers at IEDM ’13

Posted by on December 16, 2013
In Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , ,

FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI […]

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