ASN
Industry Buzz

INDUSTRY BUZZ

  • April 9, 2014 - After a very successful first edition in 2013, the 2014 IEEE S3S will take place in San Francisco, 6-9 October, 2014 (click here for details). IEEE S3S combines the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, and adds a parallel track in 3D Integration. The technical sessions will be preceded by two one-day Tutorial Short Courses.... Read more »
  • April 9, 2014 - The University of Washington’sNanofabrication Facility(WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at... Read more »
  • April 9, 2014 - A year after announcing theindustrialization of CEA-Leti’s breakthrough M&NEMS technologies, Tronics has successfully designed and manufactured the first batch of six-degrees-of-freedom (6DOF) MEMS chips, with 3 accelerometers and 3 gyroscopes on a single die (press release here). Built on SOI wafers, with a die size of less than 4mm2, this 6DOF MEMS chip is one of the smallest in... Read more »
  • March 26, 2014 - A new SemiWiki post by Dr. Eric Esteve of IPnest entitled, The Technology to Continue Moore’s Law… (click here to read it) argues that FD-SOI is the right choice. He explores cost and manufacturing considerations, and looks at the design issues in logic, memories and analog. A highly recommended... Read more »
  • March 26, 2014 - (Courtesy: SEH, weSRCH) - A presentation by Shin‐Etsu Handotai (SEH, the world’s largest wafer supplier) detailing the company’s line-up of wafers for FD-SOI and SOI-FinFET is now available on weSRCH (click here to access it). - SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since 1988. In 1997, SEH introduced SOI... Read more »
  • March 26, 2014 - (Courtesy: CEA-Leti) - Eveon and CEA-Leti have demonstrated liquid-pumping for smart drug delivery in the bolus mode using a silicon-based micro-pump fabricated with a standard MEMS process. (Read full press release here.) - The milestone is the first functional micro-pump integration using MEMS standard process on Leti’s 200mm line. It is a result of FluMin3, Eveon and Leti’s... Read more »
  • March 19, 2014 - (Image courtesy: SEMI, Soitec, weSRCH) - An excellent Soitec presentation from Semicon Japan entitled Innovative Substrates in the Mobile Era is now available on weSRCH (click here to view it). Given by Soitec COO Paul Boudre, it details the role of SOI wafers in RF and FD-SOI for... Read more »
  • March 19, 2014 - For the first time, SEMICON Europa will be held in Grenoble, France. The greater Grenoble region is home to industry leaders leveraging and researching SOI and related advanced substrates, including Soitec, Leti and ST. - SEMI has now announced the “Call for Papers” for technical sessions and presentations for SEMICON Europa 2014, which takes place October 7-9. Technical... Read more »
  • March 19, 2014 - A powerful, detailed article in EETimes-Asia details how FD-SOI Supports Moore’s Law (click here to read it). Written by Laurent Remont, ST’s VP and GM for Technology and Product Strategy, Embedded Processing Solutions,it explores FD-SOI’s advantages in terms of price, power and performance versus planar bulk CMOS and FinFETs and 28nm and 14nm. - Remont explains how structurally... Read more »
  • February 28, 2014 - Soitec Sr. VP (and FD-SOI wafer guru) Christophe Maleville has written a very good, high-level piece in the Global Semiconductor Alliance (GSA) Forum. Entitled Technology Selection Implications Intensify and Options are Limited, the piece examines cost-per-gate trends and explores roadmap options. He shows how FD-SOI provides a path forward with continued scalability, significant cost... Read more »
  • February 28, 2014 - Semiwiki blogger Paul McLellan has written an excellent piece on the FD-SOI analog-to-digital converter (ADC) that ST presented recently at ISSCC. (Read the article here.) He notes, “This is a very high performance ADC and thus an example of complex high-precision analog design in FD-SOI.” He concludes, “Together with the low-power capability of the 28nm CMOS UTBB FDSOI... Read more »
  • February 28, 2014 - Altatech, a CVD/equipment subsidiary of SOI wafer leader Soitec, announced a new collaborative partnership to research and develop materials for the next generation of high-efficiency solar cells. Joining forces with Helmholtz-Zentrum Berlin für Materialien und Energie (HZB), a member of the Helmholtz Association of German Research Centres, Altatech will be working on new classes of... Read more »
  • February 20, 2014 - (Courtesy: Synopsys, STMicroelectronics, ARM) - An excellent ARM TechCon 2013 video on FD-SOI for designers is now posted on the Synopsys site. David Jacquet from ST shares the company's FD-SOI approach to delivering optimized energy efficient solutions for the SoC market. Jacquet currently leads ST's architecture activities for energy efficient high performance CPU/GPU implementations.... Read more »
  • February 20, 2014 - Citing SOI in the Power family of high-performance processors, Chipworks concludes that IBM is a major source of chip innovation. In a recent EETimes article (read it here), which charts IBM developments at the transistor level over the last decade, the article notes that “..the 32 nm technology used to fabricate the IBM Power7+ represents an extraordinary technical achievement. IBM... Read more »
  • February 20, 2014 - “High performing low power digital technology based on SOI” is an important part of the detailed plan submitted February 14th by the Electronics Leaders' Group (ELG) to European Commission Vice-President Neelie Kroes. (Press release here.) The group recommends the EU focus on: - Areas were Europe is strong – automotive, energy, industrial automation and security. The target is to... Read more »

Latest posts
Back-biasing for FD-SOI – a simple way to meet power/performance targets Thumbnail

Back-biasing for FD-SOI – a simple way to meet power/performance targets

Posted by on November 2, 2013
In Design & Manufacturing, Editor's Blog
Tagged with , , , , ,

FD-SOI with back-biasing* (BB – also referred to as body-biasing) is an immensely powerful tool, especially for getting great performance at very low voltages with extremely low leakage. Implemented on a smartphone processor, it’s what would give you that extra day of battery life or get you to 3GHz. But what does it mean for […]

Continue ReadingLeave a Comment
IP Value Starts at the Substrate Level Thumbnail

IP Value Starts at the Substrate Level

Posted by on October 19, 2013
In News & Viewpoints, SOI In Action
Tagged with , , , , , , , , , , , , , , , , , , , ,

If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level. Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ […]

Continue ReadingLeave a Comment
Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest Thumbnail

Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest

Posted by on October 14, 2013
In Design & Manufacturing, Editor's Blog
Tagged with , , , , , , , , , , , , , , ,

Another RF-SOI solution is making headlines. Leveraging SOI, Toshiba has announced an SP10T RF antenna switch for the smartphone market. The company says it achieves the industry’s lowest insertion loss and smallest size. The company credits its new generation TaRF5 process, the latest in its line of Toshiba-original TarfSOI™ (Toshiba advanced RF SOI) processes. The […]

Continue ReadingLeave a Comment
Peregrine Semi’s RF Chip On Bonded SOS Is Main Antenna Switch in Samsung Galaxy S4 LTE-A  – That’s SOI! Thumbnail

Peregrine Semi’s RF Chip On Bonded SOS Is Main Antenna Switch in Samsung Galaxy S4 LTE-A – That’s SOI!

Posted by on September 26, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , , ,

Peregrine has announced that the company’s new UltraCMOS antenna switch is driving RF performance in the Samsung Galaxy S4 LTE-A smartphone. UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec. The new dual SP7T Multiswitch in the Samsung leverages Peregrine’s latest version of its UltraCMOS® process technology, STeP8 for RF […]

Continue ReadingLeave a Comment
SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

Continue ReadingLeave a Comment