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ST-Ericsson’s 28nm FD-SOI SmartPhone/Tablet Chip at Vegas – a Great Start to 2013 Thumbnail

ST-Ericsson’s 28nm FD-SOI SmartPhone/Tablet Chip at Vegas – a Great Start to 2013

Posted by on January 14, 2013
In Editor's Blog
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What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013. And it’s a game changer – for users, for designers, for foundries, and for …

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The Transition to Fully Depleted Thumbnail

The Transition to Fully Depleted

Posted by (SOI Industry Consortium) on December 12, 2012
In ASN #20, Special supplement: SOI Industry Consortium
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The SOI Industry Consortium is actively engaged in supporting the industry’s transition to fully-depleted (FD) technologies. FD technologies offer: better electrostatics, so you’ve got stronger gate control; and lower channel doping, which enables better SRAMs that can operate stably at lower supply voltages – resulting in power savings of up to 40%. There are two …

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Want Silicon Proof? Check Out the Fully-Depleted Tech Symposium During SF/IEDM Thumbnail

Want Silicon Proof? Check Out the Fully-Depleted Tech Symposium During SF/IEDM

Posted by on December 4, 2012
In Editor's Blog
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If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium. As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? FinFET? The Consortium’s …

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IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value Thumbnail

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value

Posted by (IBM) on November 30, 2012
In Advanced Substrate Corners, ASN #20, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
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FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, …

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Which wafers for energy-efficient, fully-depleted transistor technologies? Thumbnail

Which wafers for energy-efficient, fully-depleted transistor technologies?

Posted by (Soitec) on November 21, 2012
In ASN #20, Design & Manufacturing, In & Around Our Industry
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To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher …

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