Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.

397604-ibm-power8PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors. Reporting on this year’s Hot Chips conference, presented there. He noted that the chip “will have 12 cores, each capable of running up to eight threads, with 512KB of SRAM Level 2 cache per core (6MB total L2) and 96MB of shared embedded DRAM as a Level 3 cache.” He cites the eDRAM, which ASN readers first learned about in an ’06 article by Subi Iyer, the IBM father of eDRAM – when he explained, “The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs.”

Miller also says, “Compared with the previous generation Power 7+, which was manufactured on a 32nm SOI process, Power8 should have more than twice the memory bandwidth at 230GBps. IBM says each core should have 1.6 times the performance of Power7 on single-threaded applications and twice the SMT (symmetric multi-threaded) performance.”

Posted August 31, 2013   -   Share this Buzz

Design wins in smartphones from LG and Pantech are among the many announcements from Peregrine Semi over the last three months. These are thanks to the latest version of its UltraCMOS® process technology, STeP8 for RF Front End ICs. (The UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec.) Here’s a rundown of the recent announcements:

Posted August 30, 2013   -   Share this Buzz

Cambridge CMOS Sensors (CCMOS) says it is seeing increasing sales of its gas-sensing microsystems and is on the cusp of more major contracts. Gas-sensing technology has a broad range of applications, including domestic gas detectors, industrial safety, explosive detection, medical diagnostics and environmental monitoring. A Cambridge University spin-off that recently raised an additional £4.5m, the company was just named “Start-up of the Year” by BusinessWeekly.

Its sensors use high-temperature tungsten MOSFET heaters embedded in an SOI membrane. These effectively form a micro-hotplate that heats the sensing material, allowing it to react with gas molecules. Crucially, CCMOS’ MOSFETs can be fabricated in a commercial SOI-CMOS process and therefore can be fully integrated with the associated drive/detection circuitry. The devices can be heated from room temperature to 700°C in a fraction of a second and have the ultra-low power consumption suitable for battery operation.

Posted August 26, 2013   -   Share this Buzz

CissoidA leader in devices for extreme temperatures (-55°C to +225°C), Cissoid continues rolling out new SOI-based products for power management, power conversion and signal conditioning. Additions over the last year include:

  • FUJI, a High Reliability 3.5W DC-DC Converter with Triple Output 5V, 3.3V & 1.8V
  • CHT-RIGEL, a High Reliability Adjustable Voltage Regulator for up to 30V input and 100mA output
  • AMALTHEA, a High-Temperature, General Purpose 80V / 3A Dual Diode
  • OPAL, A High-Precision Dual Op Amps for up to 175°C and 225°C Applications.
  • A High-Temperature N-Channel MOSFET Transistor 80V / 1A in a Tiny SMD Package
  • VOLGA, a High-Temperature, High-Speed, Rail-to-Rail Comparator in a Tiny TDFP Package

Cissoid products are used in mission-critical systems as well as in applications requiring long term reliability (most will even operate over a record temperature range of 500°C). The company, which in recent months has also announced additional distribution channels, supplies leaders in the Oil&Gas, Aeronautics, Industrial and Automotive markets.

Posted August 26, 2013   -   Share this Buzz

With the upcoming Hybrid Memory Cube (HMC) from Micron et al, SOI becomes an integral part of 2.5D and 3D stacks, notes SemiMD’s Ed Sperling. “The logic base layer—in this case made by IBM—uses an SOI substrate,” he explains, “…even if some of the other pieces use different materials.” He goes on to say that while the next-gen HMC enters production at the end of next year, in the meantime the existing HMC architecture can be attached to FPGAs, either in a vertical stack or in a 2.5D configuration. “Having an additional layer of insulation is a bonus in that architectural arrangement, as well, to buffer against a variety of physical effects ranging from noise to heat.”

Posted August 16, 2013   -   Share this Buzz

MagnaChip and the National Nano Fab Center (“NNFC”) have entered into an SOI RF CMOS technology transfer agreement that combines MagnaChip’s specialty manufacturing expertise with NNFC’s robust RF technology. The two companies have targeted expansion into the emerging RF front-end module (“FEM”) foundry market.

Posted August 16, 2013   -   Share this Buzz

Digitimes reports that Vanguard International Semiconductor Corporation (VIS) has developed a 0.35-micron SOI process for manufacturing automotive chips on 8-inch wafers. The chips are currently in verification with electronics suppliers in Europe, the US and Japan.

Posted August 16, 2013   -   Share this Buzz

SiT_TempFlat_MedResSiTime, which leverages SOI for high-performance MEMS timing solutions, has introduced TempFlat™ MEMS. Until recently, all MEMS oscillators used compensation circuitry to stabilize the output frequency over temperature. SiTime’s TempFlat MEMS is a revolutionary breakthrough that eliminates temperature compensation, resulting in dramatically higher performance, smaller size, lower power and cost, says the company. According to the industry research firm Yole Développement. the silicon MEMS oscillator market is expected to grow at a CAGR of 60% to $467M in 2018 and is one of the top three growth areas in the MEMS industry

Posted July 11, 2013   -   Share this Buzz

More than 65 percent of substrates used in fabricating switches for handsets are SOI based, according to the industry research firm Yole Développement. This shows the massive adoption of RF SOI for this booming electronic market experiencing double-digit growth.  Soitec, the world’s leading manufacturer of SOI wafers, says that this shows that SOI-based technologies are now mainstream for manufacturing switches and antenna-tuners, key RF components used in all cell phones and tablet computers.

An RF SOI substrate has an active layer on which CMOS transistors are built, isolated from a high-resistivity silicon base layer. This reduces noise and interference, helping the finished die reach its target performance in terms of signal integrity, handling RF power and integration density. SOI technologies enable devices to reach a figure of merit for on-series resistance and off-equivalent capacitance (Ron.Coff ) below 200 fs (femtoseconds) with potential for further reduction. This directly relates to improved device performance and smaller die size.

On the strength of recent demonstrations, Soitec indicates that power amplifiers will likely be the next RF components based on SOI. The technology enables highly tunable amplifiers to address multi-region requirements on a single platform. In addition, the RF SOI substrates offer a path towards further integration, such as more mixed-signal and digital content.

Posted July 11, 2013   -   Share this Buzz

STMicroelectronics says its new manufacturing process, known as H9SOI_FEM, allows production of complete integrated front-end modules. This process is an evolution of the H9SOI SOI process, a groundbreaking technology introduced by ST in 2008 and subsequently used by customers to produce more than 400 million RF switches for mobile phones and Wi-Fi applications. Building on that experience, ST has optimized H9SOI for creating integrated front-end modules, resulting in today’s announcement of H9SOI_FEM offering the industry’s best figure of merit for antenna switch and antenna tuning devices with Ron x Coff at 207fs2 . ST has also invested to ensure suitable manufacturing capacity for even the most demanding of customers. The new process greatly reduces size of multi-band radios for 4G and other high-speed wireless connections.

The H9SOI_FEM process is a 0.13µm technology with dual-gate 1.2V and 2.5V MOSFETs. Unlike conventional SOI processes, such as those used for discrete devices like RF switches, H9SOI_FEM supports multiple technologies such as GO1 MOS, GO2 MOS, and optimized NLDMOS. This allows H9SOI_FEM to support full monolithic integration of all key functions of an RF front end, which comprise RF switches, Low Noise Amplifier (LNA), multi-mode multi-band cellular Power Amplifiers (PAs), diplexers, RF coupling, antenna tuning and RF energy-management functions.

H9SOI_FEM is suitable both for devices targeting the low end of the market, where low cost and extensive integration are crucial, as well as the high-end smartphone segment. High-end products typically require a combination of many frequency bands to support not only 2G, 3G and 4G standards, but also various other wireless connectivity standards such as Bluetooth, Wi-Fi, GPS and NFC (Near-Field Communication) for contactless payments.

Posted June 28, 2013   -   Share this Buzz

AMD has made two new 32nm SOI-based product announcements:

Posted June 21, 2013   -   Share this Buzz

Under a new agreement, Rambus will have access to ST’s FD-SOI process-technology design environment. With this, Rambus will be able to benefit from FD-SOI’s reduced silicon geometries and lower power consumption at 28nm and below in its future memory and interface solutions. This is part of a comprehensive agreement between the two companies, which covers FD-SOI design, security, and memory and interface technologies and settles all outstanding claims.

Posted June 21, 2013   -   Share this Buzz

FleX-Silicon-on-Polymer-ICAmerican Semiconductor has announced the FleX-MCU™ product family. Leveraging an SOI starting wafer, the FleX-MCU is the world’s first physically flexible microcontroller fabricated using the FleX™ Silicon-on-Polymer™ process. The FleX-MCU is an 8-bit RISC microcontroller with 8KB embedded RAM operating up to 20MHz, and is the initial product for a full portfolio of physically flexible ICs. The FleX IC roadmap includes microcontrollers, analog-to-digital converters (ADC), radio frequency (RF) wireless communications, and non-volatile memory (NVM).

“The Silicon-on-Polymer process can be applied to a variety of standard SOI wafers from any commercial wafer foundry or IDM. The FleX-MCU demonstrates a standard foundry process used to develop physically flexible FleX ICs. This means customers can create their own custom FleX ICs in addition to using our catalog products,” said Rich Chaney, General Manager of American Semiconductor

The FleX-MCU is fabricated in TowerJazz Semiconductor’s CS13 process. The CS13 PDK can be used to design flexible ICs; the IP blocks used in the FleX-MCU are available from American Semiconductor for customers to include in their custom designs.

In a previous announcement, Dr. Marco Racanelli, Sr. Vice President of TowerJazz said, “FleX is a post-fabrication process that can be applied to our production SOI technology making it possible to turn any product into a flexible die helping our customers create new, differentiated solutions. We are excited to partner with American Semiconductor and look forward to jointly participate in the growth of this new market.”

Posted June 17, 2013   -   Share this Buzz

Scellpicture-240Soitec has announced the industry’s first four-junction solar cell for concentrator photovoltaic (CPV) systems, entering the industry’s roadmap at a world-class level with 43.6 % efficiency. Soitec is best known as the world’s leading producer of SOI wafers for microelectronics. For the new generation of optimized III-V-based multi-junction solar cells, Soitec has leveraged its proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies and collaborated with Fraunhofer and Leti.

Soitec’s CPV modules are built on Concentrix technology, using Fresnel lenses to concentrate sunlight 500 times and focus it onto the tiny, highly-efficient multi-junction solar cells. Different types of solar cells are stacked on top of one another, with each cell type designed to convert a certain range of the solar spectrum: short wave radiation, medium wave radiation and infrared. The current generation of this technology is triple junction, achieving module efficiency of 30% — almost twice as high as the efficiency of conventional silicon photovoltaic modules.

To reach 43.6 % efficiency, Soitec’s innovative new four-junction cell uses two new, highly sophisticated dual-junction sub cells grown on different III-V compound materials, which allows optimal band-gap combinations tailored to capture a broader range of the solar spectrum. This maximizes energy-generating efficiency, and puts the company on track to be the first to reach the target of a 50% cell efficiency level.

Posted June 10, 2013   -   Share this Buzz

SOI and other advanced substrate based technologies will be significant beneficiaries of the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In addition to the recently announced €360M FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe), other projects announced by the ENIAC JU* include:

  • E450EDL (“European 450mm Equipment Demo Line”, €205.7M, 43 members) – this project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition.
  • AGATE (“Development of Advanced GaN substrates & Technologies”, €59.6M, 10 members, lead by Soitec) The project plans to set-up three pilot lines for GaN-based advanced substrates and devices to help the introduction and market acceptance of these More-Than-Moore technologies.
  • Lab4MEMS (“LAB FAB for smart sensors and actuators MEMS”, €28.5M, 21 members, lead by ST) aims to establish a European Pilot Line targeting the market drivers in consumer and healthcare application such as body area sensors and remote monitoring.

As European Commission Vice President Neelie Kroes said, “I want to double our chip production to around 20% of global production. […] It’s a realistic goal if we channel our investments properly.”

*The ENIAC Joint Undertaking (JU) is a public-private partnership focusing on nanoelectronics that brings together ENIAC Member/Associated States, the European Commission, and AENEAS (an association representing European R&D actors in this field). The document providing details on the pilot line projects is available here.

Posted June 6, 2013   -   Share this Buzz