Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
ST has signed a new foundry for 28nm FD-SOI manufacturing, but isn’t yet saying who it is.
In a press release issued with the STMicroelectronics’ 2014 First Quarter Financial Results (read press release here), Jean-Marc Chery, Executive Vice President and General Manager, Embedded Processing Solutions, said, “We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assures the industry of high-volume production of ST’s FD-SOI based IC solutions for faster, cooler, and simpler devices and strengthens the business and financial prospects of the Embedded Processing Solutions Segment.”
During the subsequent call with analysts (transcript on Seeking Alpha here), CEO Carlo Bozotti added that, “ST’s unique FD-SOI technology is well on its way to become a significant revenue generator for 2015 and beyond….”Posted April 30, 2014 - Share this Buzz
To date, over 40 readers have commented on Handel Jones’ (IBS) EETimes post entitled FinFETs Not the Best Silicon Road (read post here). He noted that, “…next-generation 20nm bulk high-K metal gate CMOS and 16/14nm FinFET process will deliver smaller transistors. However, they will also have a higher cost per gate than today’s 28nm bulk HKMG CMOS…”. He then went on to say, “One option […] is fully depleted silicon-on-insulator (FD SOI). It gives lower cost per gate and lower leakage than bulk CMOS and FinFETs.”Posted April 30, 2014 - Share this Buzz
Synopsys has announced that STMicroelectronics has standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization. As noted in the press release (read here) ST has a unique processor architecture made possible through their FD-SOI process technology. An FD-SOI device can operate at significantly higher frequencies than an equivalent, traditional, bulk CMOS device. It can also run very fast at low voltages, providing much higher energy efficiency. The close collaboration between the ST design teams and Synopsys has led to a compelling implementation solution that fully exploits the performance and power promise of FD-SOI technology and provides the throughput needed to meet tight time to market windows.Posted April 25, 2014 - Share this Buzz
A team from King Abdullah University of Science and Technology (Saudi Arabia) has published an article in Advanced Materials (22 February 2014) entitled Flexible and Transparent Silicon-on-Polymer Based Sub-20 nm Non-planar 3D FinFET for Brain-Architecture Inspired Computation. As subsequently described in an article in Nanowerk (article here), “…the team demonstrates a pragmatic approach to transforming silicon-on-insulator (SOI) based state-of-the-art FinFET into flexible and semi-transparent silicon-on-polymer FinFET while retaining high performance and integration density.” This marks the industry’s first FinFET layer transfer, team member Dr. Muhammad Mustafa Hussain told ASN.
Reproduced with permission
An industry standard 8′′ SOI wafer based ultra‐thin (1 μm), ultra‐light‐weight, fully flexible and remarkably transparent state‐of‐the‐art non‐planar three dimensional (3D) FinFET is shown. It has sub‐20 nm features and the highest performance ever reported for a flexible transistor. (Courtesy: WILEY-VCH Verlag GmbH, Advanced Materials and King Abdullah University of Science and Technology. Reprinted with permission.)Posted April 25, 2014 - Share this Buzz
Altatech, a subsidiary of Soitec, has received an order for its Orion LedMax wafer inspection and metrology system from OSRAM Opto Semiconductors GmbH, one of the world’s leading manufacturers of opto electronic components (read press release here). OSRAM will use the tool to improve the performance, cost efficiency and yield of its LED-processing operations. The leading-edge inspection system, suitable for both volume manufacturing and R&D applications, will perform production control and new product qualification of OSRAM’s epitaxial wafers used in fabricating LEDs.
Best known to many as the world leader in SOI wafer manufacturing, Soitec’s other divisions are also leaders in their areas, with wafer manufacturing equipment and products related to LEDs and solar (CPV) technology.Posted April 25, 2014 - Share this Buzz
After a very successful first edition in 2013, the 2014 IEEE S3S will take place in San Francisco, 6-9 October, 2014 (click here for details). IEEE S3S combines the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, and adds a parallel track in 3D Integration. The technical sessions will be preceded by two one-day Tutorial Short Courses. Fundamental Classes are also offered. The Call for Papers submission deadline has been set for 5 May 2014 (click here for more info).Posted April 9, 2014 - Share this Buzz
The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates matching those of more conventional CVD techniques. The system will be used by both internal and external researchers in fabricating a broad range of semiconductor-based devices including leading-edge CMOS transistors, MEMS, ICs built with the latest in through-silicon-via (TSV) technology, advanced LEDs and solar cells. Altatech is a subsidiary of Soitec (the world leader in SOI wafer manufacturing). AltaCVD systems have been used extensively in R&D and pilot production facilities throughout Europe; however, the University of Washington’s order represents the first such system to be delivered to a North American university R&D and pilot production facility.
Dr. Michael Khbeis, acting director of the WNF, said, “The AltaCVD system provides a unique capability that enables researchers to deposit conformal metal films for TSV applications as well as metal oxides and nitrides for high-k dielectrics and piezoelectric materials. The higher deposition rate enabled by pulsed CVD makes ALD films a tractable solution for scale-up paths toward high-volume manufacturing for our researchers and industrial clients. This ensures a viable pathway from academia to real economic impact in our region.”Posted April 9, 2014 - Share this Buzz
A year after announcing the industrialization of CEA-Leti’s breakthrough M&NEMS technologies, Tronics has successfully designed and manufactured the first batch of six-degrees-of-freedom (6DOF) MEMS chips, with 3 accelerometers and 3 gyroscopes on a single die (press release here). Built on SOI wafers, with a die size of less than 4mm2, this 6DOF MEMS chip is one of the smallest in the industry, and Tronics says further optimization will make it the smallest. Besides its size advantage, the piezoresistive nanowire based technology significantly decreases power consumption and allows manufacturing of all sensor types (accelerometers, gyroscopes, magnetometers, pressure sensor and microphone) using a common process flow.
This first functional batch is an important milestone towards high volume production. The industrialization work will continue through 2014, with the first commercial samples available in Q4 2014. An ASIC is also being designed and will be available in 2014 to complete the sensor platform. In addition to the 6DOF device, Tronics has also designed a very compact 9DOF monolithic MEMS. Samples will be available by the end of this year.
Target applications for this new generation of inertial devices are those where size and/or power are key: wearable devices, smartphones and tablets.Posted April 9, 2014 - Share this Buzz
A new SemiWiki post by Dr. Eric Esteve of IPnest entitled, The Technology to Continue Moore’s Law… (click here to read it) argues that FD-SOI is the right choice. He explores cost and manufacturing considerations, and looks at the design issues in logic, memories and analog. A highly recommended read.Posted March 26, 2014 - Share this Buzz
(Courtesy: SEH, weSRCH)
A presentation by Shin‐Etsu Handotai (SEH, the world’s largest wafer supplier) detailing the company’s line-up of wafers for FD-SOI and SOI-FinFET is now available on weSRCH (click here to access it).
SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since 1988. In 1997, SEH introduced SOI wafers produced using Soitec’s Smart CutTM technology. (Soitec is the world leader in SOI wafer production.) In 2012, the two companies extended their licensing agreement and expanded their technology cooperation.
The SEH presentation on weSRCH was presented in Shanghai in October 2013. The company reiterated that it has achieved the quality, has the requisite experience, and has enough factories for rapid expansion.Posted March 26, 2014 - Share this Buzz
Eveon and CEA-Leti have demonstrated liquid-pumping for smart drug delivery in the bolus mode using a silicon-based micro-pump fabricated with a standard MEMS process. (Read full press release here.)
The milestone is the first functional micro-pump integration using MEMS standard process on Leti’s 200mm line. It is a result of FluMin3, Eveon and Leti’s three-year joint-development project to produce an automatic drug-delivery system integrating a MEMS micro-pump that reduces patient discomfort by delivering medicine with very high accuracy, minimal loss and high flow rates.
The micro-pump is based on core technology initiated by Eveon and IMEP-LAHC. The pump demonstrator is made from SOI wafers, which include a thin deformable membrane sealed over a fluidic cavity and fluidic valves determining inlet and outlet. A dedicated electromagnetic actuator developed by Cedrat Technologies shapes the membrane.Posted March 26, 2014 - Share this Buzz
(Image courtesy: SEMI, Soitec, weSRCH)
An excellent Soitec presentation from Semicon Japan entitled Innovative Substrates in the Mobile Era is now available on weSRCH (click here to view it). Given by Soitec COO Paul Boudre, it details the role of SOI wafers in RF and FD-SOI for mobile.Posted March 19, 2014 - Share this Buzz
For the first time, SEMICON Europa will be held in Grenoble, France. The greater Grenoble region is home to industry leaders leveraging and researching SOI and related advanced substrates, including Soitec, Leti and ST.
SEMI has now announced the “Call for Papers” for technical sessions and presentations for SEMICON Europa 2014, which takes place October 7-9. Technical presentation abstracts are due April 30
SEMICON Europa (www.semiconeuropa.org) will highlight — in addition to the traditional semiconductor manufacturing segment — new areas like electronic components and design as well as electronic applications for energy efficiency, imaging, healthcare and security. Many of these technologies are emerging from the innovative companies in and around Grenoble. Last summer, the French government said that the new Nano2017 would make Grenoble one of the three pillars (along with what could be considered the other European SOI capitals: Dresden/GlobalFoundries and Eindhoven/NXP) of the European Horizon2020 program, which launched in January 2014 (read about that here).
The Grenoble region, with established and emerging technology companies, has been characterized as “one of the Top 5 most innovative areas in the world” by Forbes Magazine. From now on, Semicon Europa will be rotating between Dresden and Grenoble.Posted March 19, 2014 - Share this Buzz
A powerful, detailed article in EETimes-Asia details how FD-SOI Supports Moore’s Law (click here to read it). Written by Laurent Remont, ST’s VP and GM for Technology and Product Strategy, Embedded Processing Solutions, it explores FD-SOI’s advantages in terms of price, power and performance versus planar bulk CMOS and FinFETs and 28nm and 14nm.
Remont explains how structurally it is the most cost-effective sub-30nm process technology because FD-SOI is much simpler. In an interesting twist, he goes on to describe how forward body biasing (FBB) allows for dynamic power / leakage / frequency tuning linked to datacenter load. “With this, energy use would be proportional to workload and FD-SOI could reduce global data center power by up to 50 per cent,” he says.
In terms of performance, he says, “…the switch from 28nm Bulk CMOS to 28nm FD-SOI can improve circuit speed by as much as 35%. Even with this performance, FD-SOI transistors run cooler, because of lower leakage, wider voltage scaling and FBB all leading to higher power efficiency.
He concludes that FD-SOI will enable the industry to validate Moore’s Law down to 10nm. A highly recommended read.
Soitec Sr. VP (and FD-SOI wafer guru) Christophe Maleville has written a very good, high-level piece in the Global Semiconductor Alliance (GSA) Forum. Entitled Technology Selection Implications Intensify and Options are Limited, the piece examines cost-per-gate trends and explores roadmap options. He shows how FD-SOI provides a path forward with continued scalability, significant cost advantage and execution risk reduction vs. all other options. (Read the article here – GSA membership not required.)
Posted February 28, 2014 - Share this Buzz