Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.

A new SemiWiki piece by Eric Esteve heralds Fujitsu’s 14nm FD-SOI benchmark results for a high-performance networking chip (click here to read the post). In “If you still think that FDSOI is for low performance IC only…”, Esteve explains why power is critical in these high-end ASICs. He then leads readers through the benchmark results and design considerations recently posted by Fujitsu Europe’s Chief Engineer in the LinkedIn “FD-SOI design community” group (LinkedIn members can click here to join the group).  As Esteve notes, “…the great improvement on maximum power consumption on FDSOI technology is clearly due to the forward body bias effect, and such an improvement is a great benefit for high performance chips.” A highly-recommended read.

Posted February 18, 2014   -   Share this Buzz


Peregrine’s UltraCMOS® Global 1, the first reconfigurable RFFE system, includes a multimode, multiband power amplifier, post-PA switch, antenna switch and antenna tuner on a single chip. (Image courtesy: Peregrine Semiconductor)

RF-SOI powerhouse Peregrine Semiconductor has announced the Global 1 (press release here), billed as “the industry’s first reconfigurable RF front-end system”.  The company says it features the industry’s first LTE CMOS PA with the same raw performance as the leading gallium arsenide (GaAs) PAs and has a 33-percent efficiency increase over other CMOS Pas.

Peregrine notes that this platform leverages 25 years of RF expertise with proven performance demonstrated by more than 2 billion RF-SOI units shipped.

Posted February 7, 2014   -   Share this Buzz


(Images courtesy: Debiotech)

Debiotech has debuted the JewelPUMP2, a new product dedicated to the Diabetes Type 2 market, based on Debiotech’s innovative JewelPUMP platform (press release here). By using its JewelPUMP platform, which is already in the industrialization phase and in preparation for the CE marking, Debiotech will be able to introduce the JewelPUMP2 shortly after its JewelPUMP for Type 1 patients, while ensuring the same degree of miniaturization, safety and reliability.

Back in 2009, Debiotech wrote in ASN (click here to read the article) about their Nanopump™, a volumetric membrane pump, at the heart of their systems. Co-designed by Debiotech and ST, and manufactured by ST, the pump consists of a membrane micromachined in an SOI wafer, which is in turn sandwiched between two Pyrex™ plates with throughholes. A piezoelectric actuator moves the membrane to compress and decompress the fluid in the pumping chamber.

Posted February 7, 2014   -   Share this Buzz


(Courtesy: SiTime)

The extreme reliability of SiTime’s MEMS devices, using SOI technology, has enabled the company to cover all its MEMS oscillators and clock generators with a lifetime warranty (press release here).

SiTime contributed an excellent article to ASN a few years ago (click here to read it), explaining how their radical SOI-based approach put the company at the top of the fast-growing silicon-based timing market.

Now, SOI plus excellent design, quality, manufacturability and reliability, has enabled the company to cover all its MEMS oscillators and clock generators with a lifetime warranty. The devices are setting new standards in quality and reliability, Piyush Sevalia,
Executive VP, Marketing at SiTime told ASN. The company has ascertained historic evidence of extremely low return failure rates (0.5 DPPM) with their SOI-based product lines.

Posted January 31, 2014   -   Share this Buzz

Europe needs to build a high-volume FD-SOI fab. Malcolm Penn, CEO of Future Horizons, said this in the firm’s annual forecast meeting, reported David Manners of ElectronicsWeekly (Click here to read his article.)

Last year, European Commission Vice President Neelie Kroes said, “I want to double our chip production to around 20% of global production. […] It’s a realistic goal if we channel our investments properly.” (Click here for more on that story.)

To meet that goal, “The cornerstone of the European Leaders Group (ELG) report to Neelie Kroes, due in a week or two, should be the construction of a high volume FD-SOI wafer fab,” said Penn, as reported by Manners.

Despite resistance from Europe’s biggest semi players, “Building a volume production FD-SOI fab would be one of the most blatantly obvious things the ELG could do,” said Penn in the Manners piece, “it should be a cornerstone of the ELG plan. It would be a fantastic thing for them to do.”

Posted January 31, 2014   -   Share this Buzz

CMPmultiwaferCMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. 
In 2013, they had 32 prototypes from 15 customers over three runs. The latest run embedded 25 different projects. Delivery of that run to users will be in Q2 2014.

“We have a total of 140 institutions/companies already using the PDK. Four MPW runs are scheduled in 2014, one for each quarter,” said Dr. Torki. MPW price is 15000 Euro/mm2.

“At CMP we fully support UTSOI model cards available in the process design-kit (PDK) for the 28nm FDSOI process,” explains Dr. Torki. The simulation model itself is available for Eldo, Spectre and Hspice. Cadence, Mentor and Synopsys make this model available as a standard feature thanks to a Leti-ST licensing agreement.

Look for news about availability of Leti’s new UTSOI2 model (click here for more information on the model) for 14nm FD-SOI in Q2.

Posted January 31, 2014   -   Share this Buzz

Taur_coverIn a new edition (2013) of Taur and Ning’s Fundamentals of Modern VLSI Devices, the authors have added a chapter on SOI devices.  The first edition of the book was widely adopted as a standard textbook in microelectronics in many major US universities and worldwide.  Reviewers on Amazon called the first edition of this book (1998) “best textbook I used” and the “Bible for microelectronic device engineers”.  Now available as an eBook as well as in hardcover and paperback from Cambridge University Press (click here for details), this new edition will also be a valuable reference volume for practicing engineers involved in research and development in the electronics industry.  As Professor Mark Lundstrom of Purdue noted, “The best book of its kind is now even better.”

A professor at UC San Diego, Yuan Taur spent twenty years at IBM’s T. J. Watson Research Center. Tak H. Ning is an IBM Fellow at the T. J. Watson Research Center, where he has worked for over 35 years.

Posted January 23, 2014   -   Share this Buzz

Fossum_coverA new book by two giants in SOI – Jerry Fossum of U. Florida/Gainesville and Vishal Trivedi of Freescale –  delves into the Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs.  Available from Cambridge University Press in both hardcover and eBook formats (click here for more information), it covers theory, design and applications of FD-SOI MOSFETs and FinFETs (you can review the Table of Contents here). The book is billed as “a must-have resource” for professional engineers in the CMOS IC field who need to know about optimal nonclassical device design and integration.

ASN readers will remember that Dr. Fossum won the IEEE/EDS J. J. Ebers Award in 2004 for ‘outstanding contributions to the advancement of SOI CMOS devices and circuits through modeling’.  They also may remember his concise, elegant argument back in 2007 (see article here) as to why SOI represents a pragmatic approach to FinFETs.

Posted January 23, 2014   -   Share this Buzz

STMicroelectronics has released details of its innovative STi8K™ architecture addressing future Systems-on-Chips (SoCs) for the Digital Home (press release here).  Optimized for ST’s 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) and smaller-geometry manufacturing processes, the STi8K™ architecture leverages the increased data throughput, the extended memory addressing, and the reduced power consumption of the latest ARM® Cortex™-A53 and Cortex™-A57 64-bit processor technology, combining high performance and reliability with outstanding energy efficiency.

“The consumer industry has initiated the transition from 32- to 64-bit computing in the mobile market,” said Gian Luca Bertino, Executive Vice President and General Manager Digital Convergence Group, STMicroelectronics. “New upcoming, highly demanding technologies, such as DOCSIS 3.1 or full-featured 10-bit High-Efficiency Video Coding (HEVC) in Ultra High Definition at 60 frames per second, will drive this same transition in the Digital Home market.”

Tom Cronk, Senior Vice President, Commercial Operations, at ARM added, “We share ST’s vision for the future of the digital home market. Full-color Ultra HD applications together with ultra-high bandwidth home-network-access systems made possible with DOCSIS 3.1 technologies will transform the home-entertainment experience. Our long-term collaboration with ST, including its recent integration of our latest 64-bit processors, together with our mutual investment in software-ecosystem development, are key building blocks that will help make more advanced and immersive media experiences a reality.”

Posted January 17, 2014   -   Share this Buzz

FD-SOI could be the “tipping point” for SOI, supply chain expert Bill Kohnen indicated in a presentation at the Semiconductor Technical Purchasing Conference last fall. (See his ppt here.) He suggested, “Purchasing and Supply Chain Organizations at Foundries and Device Manufacturers that need SOI wafers need to closely monitor the supply chain as demand resulting from FD-SOI applications may be the tipping point for capacity issues.”  He concludes that the industry consortiums will be helpful in avoiding a “bullwhip effect”.

Posted January 17, 2014   -   Share this Buzz

“If GLOBALFOUNDRIES has the ability to economically research, develop, and produce parts on 20 nm FD-SOI, they could be hitting one out of the park,” said Josh Walrath (citing the baseball expression for a big home run) in a long PC Perspectives article last fall (Oct. ’13). “The industry is clamoring for a product that can match the power characteristics of Intel’s 22 nm process.” In the article, entitled Next Gen Graphics and Process Migration: 20 nm and Beyond, he contends that “The Really Good Times are Over” for the breakneck advances we got use to seeing in GPUs in years past.  For his gamer audience, he clearly charts the evolutions in chip design, nodes and graphics performance.  Citing the challenges at 20nm and below, he suggest that “…FD-SOI seems like it answers most of the issues that crop up with the 22/20 nm node. It does not require massive design rule changes, it can re-use a lot of bulk silicon manufacturing technology, and it runs perfectly fine with planar transistors at 22/20 nm. In a gate-last configuration, FD-SOI with planar transistors actually looks like it outperforms and scales significantly better than Intel’s 22 nm Tri-Gate process.” A recommended read.

Posted January 17, 2014   -   Share this Buzz

Zvi-F10-12-23Following IEDM (Dec. ’13), Zvi Or-Bach, President & CEO of posted a SemiMD blog (click here) entitled Why SOI is the Future Technology of Semiconductors.  Beginning with the assertions that it’s cheaper and easier for FinFETS, it’s a natural for monolithic 3D ICs, and it best for next-gen transistor architectures, he goes on to elaborate on each of these points.   He cites presentations by GloFo and IBS for cost, then delves into Leti’s sequential 3D technology, leveraging FD-SOI and FinFETs, as well as other SOI-based monolithic 3D IC integration developments. A recommended read.

Posted January 13, 2014   -   Share this Buzz

Leti recently announced an agreement with Qualcomm Technologies, under which Qualcomm will assess the feasibility and the value of Leti’s sequential 3D technology. As opposed to 3D with TSVs, sequential 3D integration involves stacking active layers of transistors using molecular bonding. In his Electronics360 blog, Peter Clarke points out the synergies between the Leti process and FD-SOI.

Posted January 13, 2014   -   Share this Buzz

Simon Yang, the CEO of XMC, a fast growing specialty foundry in China, gave an excellent presentation about FD-SOI at the SOI Consortium’s Technology Summit in Shanghai (Oct., 2013).  The presentation is now available both through VLSI’s weSRCH site (click here) and through the SOI Consortium’s website (click here for this plus all the other Shanghai presentations).  While noting that over half of the world’s ICs are going into China, and three-quarters of them are <65nm, Yang’s looking at ways to boost his 12” utilization.

He asks if FD-SOI can be part of the solution, noting that it is a simple way to gain entry into fully-depleted technologies: it is a mature planar CMOS process, is easily portable for existing bulk designs, and is a particularly good choice for mobile markets.  Yang was formerly CTO of Chartered, which would indicate he’s familiar with SOI (pre-GloFo, Chartered produced PD-SOI chips for AMD).

While design houses in China want high performance and low power, they’ll go with whatever technology is good enough and cheap enough, he says. While he cites FD-SOI advantages, he also doesn’t pull any punches with respect to how he perceives the challenges, primarily with respect cost and ecosystem.

Posted January 13, 2014   -   Share this Buzz

eSIperformanceSoitec has issued a highly-informative new white paper on its enhanced signal integrity – aka eSI™ – wafers for 4G and LTE/A applications (to get the paper, click here).  Entitled “Innovative RF-SOI Wafers for Wireless Applications”, the paper explains the various challenges faced by RF IC designers, and how the new eSI wafers offer powerful solutions.  The substrates on which devices for LTE apps are manufactured play a major role in achieving requisite levels of performance.  They allow RF designers to integrate on the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies. As described recently in ASN (click here), the new eSI wafers are now in high-volume production, and are being used at most of the leading RF foundries.

Posted December 19, 2013   -   Share this Buzz