Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.


Bloggers for the mega Semiwiki site are warming fast to FD-SOI.  Three recent pieces have generated a lot of good comments and discussions – check them out here (links embedded):

Posted November 8, 2013   -   Share this Buzz
Peregrine Semi's new UltraCMOS 10 RF-SOI technology platform gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.(Photo: Business Wire)

Peregrine Semi’s new UltraCMOS 10 RF-SOI technology platform gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks. (Photo: Business Wire)

Peregrine Semiconductor announced that it has shipped its 2 billionth chip, released version 10 of its UltraCMOS RF-SOI technology, and is working with GlobalFoundries.

UltraCMOS technology is an advanced RF-SOI process, the latest versions of which leverage bonded silicon-on-sapphire (BSOS) substrates from Soitec. Peregrine did an excellent article for ASN last spring, clearly explaining the use of sapphire as a highly insulating substrate for RF-SOI CMOS processing.

Posted November 4, 2013   -   Share this Buzz

Good, informative read: In SemiMD, FD-SOI Targets Mobile Applications by Giorgio Cesana of
ST and Carlos Mazure of Soitec. The article explains why FD-SOI is perfectly suited for mobile IC
applications where power consumption has to be very low to maximize battery lifetime. The authors
compare the technology to planar bulk and FinFETs, touching on body-biasing, substrates, design,
and circuit results/performance.

Posted October 31, 2013   -   Share this Buzz

“…you may hear more companies than just STMicro are doing a lot of designs on FDSOI, because
in addition to cost equivalents, they get significant power savings and speed up,” Herb Reiter,
founder and president of eda2asic told EDA Cafe in a recent interview. Adding that “…FDSOI […]
design requirements are just like bulk silicon and are almost totally transparent to the designers,” he
concludes, “…consider the savings in the fab, where you have fewer process steps and less
processing time. Also, remember that with each step in manufacturing, the yield decreases – the
bottom line is that FDSOI is becoming really cost competitive for most apps.”

Posted October 31, 2013   -   Share this Buzz

“…we are ramping a large number of SOI switch designs on our industry-leading SOI process,”
noted TowerJazz CEO Russell Ellwanger in the company’s September ’13 newsletter. The SOI
switch designed in Netanya “…received impressive traction and is winning business for the RF/HPA
business unit,” adds Ori Galzur, Vice President of TowerJazz’s Worldwide VLSI Design Center. He
also notes that the design team has released STD cell libraries for their SOI platforms.

Posted October 31, 2013   -   Share this Buzz

In an interview in Semiconductor Engineering, SOI wafer leader Soitec’s Chairman and CEO
André-Jacques Auberton-Hervé addressed substrates and trends for FD-SOI, FinFETs, RF, lighting,
solar and more. He said mobile markets were driving FD-SOI, while server markets drive FinFETs.
He also said the company’s various RF offerings drove 40% of last year’s growth.

Posted October 31, 2013   -   Share this Buzz

IBM’s Watson supercomputer, which is based on SOI, has a new job in medical training. IBM
announced that the team of researchers that created Watson will work with Cleveland Clinic
clinicians, faculty and medical students to enhance the capabilities of Watson’s Deep Question
Answering technology for the area of medicine. Over time, the expectation is that Watson will get
“smarter” about medical language and how to assemble good chains of evidence from available
content.

Posted October 31, 2013   -   Share this Buzz

EETimes predicts a FD-SOI vs. FinFET showdown at the upcoming IEDM conference. At Session 9
on advanced CMOS platforms TSMC will provide details on the company’s 16nm bulk FinFET
CMOS process, followed by a paper on the 14nm FD-SOI process by STMicroelectronics, Soitec,
Leti, IBM, GlobalFoundries, and Renesas.

Posted October 31, 2013   -   Share this Buzz

CMPwafer

The prototyping services organization CMP has already received over 110 requests for the 28nm FD-SOI PDK from ST.  The requests are coming from major companies as well as R&D organizations and universities.  The CMP offering was detailed in ASN last year – click here for details. Designers are now asking CMP for ST’s 14nm FD-SOI PDK, which is expected to be available shortly.

 

Posted October 14, 2013   -   Share this Buzz

A blog on the Mentor website entitled the Battle of Fins and BOXes considers FD-SOI, FinFETs and planar bulk. The author notes, “Power/performance claims of 30% to 40% are not uncommon and FDSOI is already in production at 28nm and is positioned as an alternate option to bulk 20nm. Even if FDSOI at 28nm delivers half the power savings of bulk 20nm, I would take it any day rather than dealing with the beast that is Double Patterning. I digress. One of the other untold benefits from a P&R perspective is that the FDSOI technology can use the conventional design flows and is completely transparent to the tools.”

Posted October 14, 2013   -   Share this Buzz

ST slide, CMP wafer

An excellent, in-depth guide to FD-SOI design by ST is now freely available on the CMP website. It’s entitled UTBB-FDSOI Design & Migration Methodology and is authored by Philippe Flatresse of ST’s Central CAD & Design Solutions group. Addressing both digital and analog, he covers library migration, back-biasing, multi-Vt optimization, porting methodologies and strategies for ESD and IO.

Posted October 14, 2013   -   Share this Buzz
Solar Cell

World record solar cell with 44.7% efficiency, made up of four solar subcells based on III-V compound semiconductors for use in concentrator photovoltaics. (Photo ©Fraunhofer ISE)

III-V wafer bonding has enabled a new world record for the conversion of sunlight into electricity, announced the Fraunhofer Institute for Solar Energy Systems ISE, Soitec, CEA-Leti and the Helmholtz Center Berlin. Creating a new solar cell structure with four solar subcells, the team took the lead after only over three years of research, entering the roadmap with a new record efficiency of 44.7%. This indicates that 44.7% of the solar spectrum’s energy, from ultraviolet through to the infrared, is converted into electrical energy. This is a major step towards reducing further the costs of solar electricity and continues to pave the way to the 50% efficiency roadmap. Wafer bonding plays a central role, as it enables the connection of two semiconductor crystals that otherwise cannot be grown on top of each other with high crystal quality. This produces the optimal semiconductor combination for the highest efficiency solar cells.

A few weeks prior, Soitec announced the launched of a new solar-energy concentrated photovoltaic (CPV) module featuring 31.8% efficiency, the highest of any commercial module being mass produced today.

Posted October 1, 2013   -   Share this Buzz

STMtrophycSTMicroelectronics has won a prestigious BearingPoint Innovation Management Award for its FD-SOI technology in the “Innovation Ecosystem” category. FD-SOI was recognized as a major breakthrough in the pursuit of silicon-chip miniaturization. “STMicroelectronics strategically chose to include multiple partners at the earliest stages of their R&D program. This new digital technology was then positioned as being faster in a very competitive market,” said Eric Falque, President of BearingPoint France-Benelux.

Georges Penalver, Executive Vice President and Chief Strategy Officer at ST noted, “The fruit of scientific research, strategic vision and long-standing determination, faster, cooler and simpler FD-SOI technology strengthens ST’s role in shaping the future of the microelectronics industry. This award, like our success in delivering FD-SOI, is a major achievement for ST, its employees and its partners.”

Posted October 1, 2013   -   Share this Buzz

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, has licensed some of its intellectual property (IP) portfolio related to back-side illumination (BSI) technology for image sensors to TSMC. BSI is a key enabling technology in the race to develop small-pixel, high-quality image sensors used in consumer products such as digital cameras, smart phones and other portable electronics.  In this case, the BSI technology uses some of the key process steps of Soitec’s Smart Stacking™ generic technology.

The company also announced that it has received ISO 22301:2012 certification for its Bernin site (near Grenoble, in South-East France). This international standard provides a framework for companies in implementing procedures that will ensure the continuity of their critical businesses during exceptional circumstances. Soitec, the first ISO 22301:2012 certified company in France, has thus received recognition for the quality of its business continuity management system to protect the company from disruptive incidents (fires, unavailability of its information system, pandemics, malicious acts, etc.) by reducing their potential impact on its business.

In solar news, Soitec announced its newest concentrated photovoltaic (CPV) module featuring a record power-generating efficiency of 31.8 percent. The new module, which is already in industrial volume production, has the highest efficiency of any commercial product available for multi-megawatt installations.

Posted September 16, 2013   -   Share this Buzz

397604-ibm-power8PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors. Reporting on this year’s Hot Chips conference, presented there. He noted that the chip “will have 12 cores, each capable of running up to eight threads, with 512KB of SRAM Level 2 cache per core (6MB total L2) and 96MB of shared embedded DRAM as a Level 3 cache.” He cites the eDRAM, which ASN readers first learned about in an ’06 article by Subi Iyer, the IBM father of eDRAM – when he explained, “The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs.”

Miller also says, “Compared with the previous generation Power 7+, which was manufactured on a 32nm SOI process, Power8 should have more than twice the memory bandwidth at 230GBps. IBM says each core should have 1.6 times the performance of Power7 on single-threaded applications and twice the SMT (symmetric multi-threaded) performance.”

Posted August 31, 2013   -   Share this Buzz