Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
Design & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective.
After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk planar (28/20nm) and bulk FinFET (16/14nm). He then gives examples of ARM core IP, and how FD-SOI is leveraged in ultra-low-voltage, analog and high-speed apps.Posted November 18, 2013 - Share this Buzz
“The performance and power results on ARM processors on 28 nm FD-SOI are outstanding,” writes Josh Walrath in PC Perspectives. In a piece looking at where graphics are headed, he goes on to say, “FD-SOI seems like it answers most of the issues that crop up with the 22/20 nm node. It does not require massive design rule changes, it can re-use a lot of bulk silicon manufacturing technology, and it runs perfectly fine with planar transistors at 22/20 nm. In a gate-last configuration, FD-SOI with planar transistors actually looks like it outperforms and scales significantly better than Intel’s 22 nm Tri-Gate process.”Posted November 13, 2013 - Share this Buzz
“French research group CEA-Leti expects to have design kits ready for a 10nm fully depleted silicon-on-insulator (FD-SOI) process in June 2014, Jean-René Lequepeys, vice president of the silicon components division told Future Horizons’ International Electronics Forum in Dublin today (4 October 2014),” reports Chris Edwards in Tech Design Forum.Posted November 8, 2013 - Share this Buzz
Memoir Systems has made its revolutionary Algorithmic Memory Technology available for embedded memories in ASICs and SoCs manufactured in STMicroelectronic’s FD-SOI process technology. ST is a leading manufacturer of ASICs.
“With our commitment to breakthrough memory technology, accelerated design times, and extreme high-performance, making our best-in-class Algorithmic Memory Technology available on FD-SOI was important to us and our customers, “said Sundar Iyer, co-founder and CEO at Memoir Systems. “The ease of porting, together with the performance we’ve seen, confirms that FD-SOI is faster, cooler, and simpler.”Posted November 8, 2013 - Share this Buzz
Bloggers for the mega Semiwiki site are warming fast to FD-SOI. Three recent pieces have generated a lot of good comments and discussions – check them out here (links embedded):
- ST Endorses PowerArtist with ARM Cores & FDSOI libs (by Pawan Fangaria);
- The Alternative to FinFET: FD-SOI (by Paul McLellan);
- Is FD-SOI Smarter than Moore? (by Eric Esteve).
UltraCMOS technology is an advanced RF-SOI process, the latest versions of which leverage bonded silicon-on-sapphire (BSOS) substrates from Soitec. Peregrine did an excellent article for ASN last spring, clearly explaining the use of sapphire as a highly insulating substrate for RF-SOI CMOS processing.Posted November 4, 2013 - Share this Buzz
Good, informative read: In SemiMD, FD-SOI Targets Mobile Applications by Giorgio Cesana of
ST and Carlos Mazure of Soitec. The article explains why FD-SOI is perfectly suited for mobile IC
applications where power consumption has to be very low to maximize battery lifetime. The authors
compare the technology to planar bulk and FinFETs, touching on body-biasing, substrates, design,
and circuit results/performance.
“…you may hear more companies than just STMicro are doing a lot of designs on FDSOI, because
in addition to cost equivalents, they get significant power savings and speed up,” Herb Reiter,
founder and president of eda2asic told EDA Cafe in a recent interview. Adding that “…FDSOI […]
design requirements are just like bulk silicon and are almost totally transparent to the designers,” he
concludes, “…consider the savings in the fab, where you have fewer process steps and less
processing time. Also, remember that with each step in manufacturing, the yield decreases – the
bottom line is that FDSOI is becoming really cost competitive for most apps.”
“…we are ramping a large number of SOI switch designs on our industry-leading SOI process,”
noted TowerJazz CEO Russell Ellwanger in the company’s September ’13 newsletter. The SOI
switch designed in Netanya “…received impressive traction and is winning business for the RF/HPA
business unit,” adds Ori Galzur, Vice President of TowerJazz’s Worldwide VLSI Design Center. He
also notes that the design team has released STD cell libraries for their SOI platforms.
In an interview in Semiconductor Engineering, SOI wafer leader Soitec’s Chairman and CEO
André-Jacques Auberton-Hervé addressed substrates and trends for FD-SOI, FinFETs, RF, lighting,
solar and more. He said mobile markets were driving FD-SOI, while server markets drive FinFETs.
He also said the company’s various RF offerings drove 40% of last year’s growth.
IBM’s Watson supercomputer, which is based on SOI, has a new job in medical training. IBM
announced that the team of researchers that created Watson will work with Cleveland Clinic
clinicians, faculty and medical students to enhance the capabilities of Watson’s Deep Question
Answering technology for the area of medicine. Over time, the expectation is that Watson will get
“smarter” about medical language and how to assemble good chains of evidence from available
EETimes predicts a FD-SOI vs. FinFET showdown at the upcoming IEDM conference. At Session 9
on advanced CMOS platforms TSMC will provide details on the company’s 16nm bulk FinFET
CMOS process, followed by a paper on the 14nm FD-SOI process by STMicroelectronics, Soitec,
Leti, IBM, GlobalFoundries, and Renesas.
The prototyping services organization CMP has already received over 110 requests for the 28nm FD-SOI PDK from ST. The requests are coming from major companies as well as R&D organizations and universities. The CMP offering was detailed in ASN last year – click here for details. Designers are now asking CMP for ST’s 14nm FD-SOI PDK, which is expected to be available shortly.
Posted October 14, 2013 - Share this Buzz
A blog on the Mentor website entitled the Battle of Fins and BOXes considers FD-SOI, FinFETs and planar bulk. The author notes, “Power/performance claims of 30% to 40% are not uncommon and FDSOI is already in production at 28nm and is positioned as an alternate option to bulk 20nm. Even if FDSOI at 28nm delivers half the power savings of bulk 20nm, I would take it any day rather than dealing with the beast that is Double Patterning. I digress. One of the other untold benefits from a P&R perspective is that the FDSOI technology can use the conventional design flows and is completely transparent to the tools.”Posted October 14, 2013 - Share this Buzz
An excellent, in-depth guide to FD-SOI design by ST is now freely available on the CMP website. It’s entitled UTBB-FDSOI Design & Migration Methodology and is authored by Philippe Flatresse of ST’s Central CAD & Design Solutions group. Addressing both digital and analog, he covers library migration, back-biasing, multi-Vt optimization, porting methodologies and strategies for ESD and IO.Posted October 14, 2013 - Share this Buzz