Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.

Two SOI pioneers have been elevated to the status of Fellow by the IEEE for their extraordinary accomplishents:

  • Jean-Pierre Raskin (Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium) – joined the “Class of 2014” for “contributions to the characterization of silicon-on-insulator RF MOSFETs and MEMS devices”.  Dr. Raskin received his PhD degree from UCL, where he is a professor and head of the Microwave Laboratory.
  • Carlos Mazure (Soitec, Bernin, France) – joined the “Class of 2013” for “leadership in the field of silicon on insulator and memory technologies”. Dr. Mazure is CTO of SOI wafer leader Soitec. He has filed more than 100 patents worldwide and is the author of 120 scientific papers. He holds two PhDs in physics, one from the University of Grenoble, France, and the other from the Technical University of Munich, Germany.
Posted December 5, 2013   -   Share this Buzz

Sand 9 has debuted the TM651, an SOI-based MEMS solution that it says achieves the stringent low-noise, high-stability and harsh environmental requirements for precision timing in communications infrastructure, industrial and military applications. It is the first product based on Sand 9’s patented Temperature Compensated MEMS Oscillator (TCMO™) platform.  Sand 9 is working closely with a number of leading analog semiconductor partners to provide reference designs for their synthesizer and timing products. Peter Real, vice president, High Speed Products and Technology, Analog Devices, commented: “As a leading supplier into communications infrastructure, industrial and military markets, Analog Devices is committed to exploring technologies that may improve the experience of our customers. Having initially invested in Sand 9 late last year, we are pleased to see them launch their first precision MEMS timing product.”

Posted December 5, 2013   -   Share this Buzz

Good news for the SOI ecosystem: SOI wafer suppliers Soitec and SunEdison (formerly MEMC) have ended their longstanding legal feud and entered into a patent cross-license agreement (press release here).  The agreement provides each company with access to the other’s patent portfolio for SOI technologies and ends all their outstanding legal disputes.

For Soitec, it represents a milestone for the SOI ecosystem, said Christophe Maleville, SVP of the company’s Digital Electronics Division.

For SunEdison, it adds to the company’s current SOI product capability, said Horacio Mendez, VP of the company’s Semiconductor Advanced Solutions division.

The agreement covers wafers for device architectures such as partially-depleted SOI (PD-SOI), fully-depleted SOI (FD-SOI) and radio-frequency SOI (RF-SOI) as well as advanced FinFETs.

The two companies have also agreed to grant each other the right to use their respective wholly-owned patents for research and development purposes. This applies to the development of products with advanced semiconductor materials beyond silicon that enable the fabrication of high-mobility channels for advanced generation digital applications.

Posted November 27, 2013   -   Share this Buzz

“At 14nm FD-SOI is much cheaper, 30-40% cheaper, than Intel’s technology,” Asen Asenov told David Manners in a recent Electronics Weekly post (see full post here).  Asenov is CEO and Founder of Gold Standard Simulations (GSS).  The subject of the post was how TSMC has turned to GSS for statistical analysis tools. Professor Asenov is a fan of ST’s FD-SOI, noted Manners. The main challenge is building the ecosystem, he concluded.

Posted November 27, 2013   -   Share this Buzz

D+R_ST_FDSOIslideDesign & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective.

After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk planar (28/20nm) and bulk FinFET (16/14nm).  He then gives examples of ARM core IP, and how FD-SOI is leveraged in ultra-low-voltage, analog and high-speed apps.

Posted November 18, 2013   -   Share this Buzz

“The performance and power results on ARM processors on 28 nm FD-SOI are outstanding,” writes Josh Walrath in PC Perspectives. In a piece looking at where graphics are headed, he goes on to say, “FD-SOI seems like it answers most of the issues that crop up with the 22/20 nm node. It does not require massive design rule changes, it can re-use a lot of bulk silicon manufacturing technology, and it runs perfectly fine with planar transistors at 22/20 nm. In a gate-last configuration, FD-SOI with planar transistors actually looks like it outperforms and scales significantly better than Intel’s 22 nm Tri-Gate process.”

Posted November 13, 2013   -   Share this Buzz

“French research group CEA-Leti expects to have design kits ready for a 10nm fully depleted silicon-on-insulator (FD-SOI) process in June 2014, Jean-René Lequepeys, vice president of the silicon components division told Future Horizons’ International Electronics Forum in Dublin today (4 October 2014),” reports Chris Edwards in Tech Design Forum.

Posted November 8, 2013   -   Share this Buzz

Memoir Systems has made its revolutionary Algorithmic Memory Technology available for embedded memories in ASICs and SoCs manufactured in STMicroelectronic’s FD-SOI process technology. ST is a leading manufacturer of ASICs.

“With our commitment to breakthrough memory technology, accelerated design times, and extreme high-performance, making our best-in-class Algorithmic Memory Technology available on FD-SOI was important to us and our customers, “said Sundar Iyer, co-founder and CEO at Memoir Systems. “The ease of porting, together with the performance we’ve seen, confirms that FD-SOI is faster, cooler, and simpler.”

Posted November 8, 2013   -   Share this Buzz

Bloggers for the mega Semiwiki site are warming fast to FD-SOI.  Three recent pieces have generated a lot of good comments and discussions – check them out here (links embedded):

Posted November 8, 2013   -   Share this Buzz
Peregrine Semi's new UltraCMOS 10 RF-SOI technology platform gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.(Photo: Business Wire)

Peregrine Semi’s new UltraCMOS 10 RF-SOI technology platform gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks. (Photo: Business Wire)

Peregrine Semiconductor announced that it has shipped its 2 billionth chip, released version 10 of its UltraCMOS RF-SOI technology, and is working with GlobalFoundries.

UltraCMOS technology is an advanced RF-SOI process, the latest versions of which leverage bonded silicon-on-sapphire (BSOS) substrates from Soitec. Peregrine did an excellent article for ASN last spring, clearly explaining the use of sapphire as a highly insulating substrate for RF-SOI CMOS processing.

Posted November 4, 2013   -   Share this Buzz

Good, informative read: In SemiMD, FD-SOI Targets Mobile Applications by Giorgio Cesana of
ST and Carlos Mazure of Soitec. The article explains why FD-SOI is perfectly suited for mobile IC
applications where power consumption has to be very low to maximize battery lifetime. The authors
compare the technology to planar bulk and FinFETs, touching on body-biasing, substrates, design,
and circuit results/performance.

Posted October 31, 2013   -   Share this Buzz

“…you may hear more companies than just STMicro are doing a lot of designs on FDSOI, because
in addition to cost equivalents, they get significant power savings and speed up,” Herb Reiter,
founder and president of eda2asic told EDA Cafe in a recent interview. Adding that “…FDSOI […]
design requirements are just like bulk silicon and are almost totally transparent to the designers,” he
concludes, “…consider the savings in the fab, where you have fewer process steps and less
processing time. Also, remember that with each step in manufacturing, the yield decreases – the
bottom line is that FDSOI is becoming really cost competitive for most apps.”

Posted October 31, 2013   -   Share this Buzz

“…we are ramping a large number of SOI switch designs on our industry-leading SOI process,”
noted TowerJazz CEO Russell Ellwanger in the company’s September ’13 newsletter. The SOI
switch designed in Netanya “…received impressive traction and is winning business for the RF/HPA
business unit,” adds Ori Galzur, Vice President of TowerJazz’s Worldwide VLSI Design Center. He
also notes that the design team has released STD cell libraries for their SOI platforms.

Posted October 31, 2013   -   Share this Buzz

In an interview in Semiconductor Engineering, SOI wafer leader Soitec’s Chairman and CEO
André-Jacques Auberton-Hervé addressed substrates and trends for FD-SOI, FinFETs, RF, lighting,
solar and more. He said mobile markets were driving FD-SOI, while server markets drive FinFETs.
He also said the company’s various RF offerings drove 40% of last year’s growth.

Posted October 31, 2013   -   Share this Buzz

IBM’s Watson supercomputer, which is based on SOI, has a new job in medical training. IBM
announced that the team of researchers that created Watson will work with Cleveland Clinic
clinicians, faculty and medical students to enhance the capabilities of Watson’s Deep Question
Answering technology for the area of medicine. Over time, the expectation is that Watson will get
“smarter” about medical language and how to assemble good chains of evidence from available

Posted October 31, 2013   -   Share this Buzz