Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.


“If GLOBALFOUNDRIES has the ability to economically research, develop, and produce parts on 20 nm FD-SOI, they could be hitting one out of the park,” said Josh Walrath (citing the baseball expression for a big home run) in a long PC Perspectives article last fall (Oct. ’13). “The industry is clamoring for a product that can match the power characteristics of Intel’s 22 nm process.” In the article, entitled Next Gen Graphics and Process Migration: 20 nm and Beyond, he contends that “The Really Good Times are Over” for the breakneck advances we got use to seeing in GPUs in years past.  For his gamer audience, he clearly charts the evolutions in chip design, nodes and graphics performance.  Citing the challenges at 20nm and below, he suggest that “…FD-SOI seems like it answers most of the issues that crop up with the 22/20 nm node. It does not require massive design rule changes, it can re-use a lot of bulk silicon manufacturing technology, and it runs perfectly fine with planar transistors at 22/20 nm. In a gate-last configuration, FD-SOI with planar transistors actually looks like it outperforms and scales significantly better than Intel’s 22 nm Tri-Gate process.” A recommended read.

Posted January 17, 2014   -   Share this Buzz

Zvi-F10-12-23Following IEDM (Dec. ’13), Zvi Or-Bach, President & CEO of posted a SemiMD blog (click here) entitled Why SOI is the Future Technology of Semiconductors.  Beginning with the assertions that it’s cheaper and easier for FinFETS, it’s a natural for monolithic 3D ICs, and it best for next-gen transistor architectures, he goes on to elaborate on each of these points.   He cites presentations by GloFo and IBS for cost, then delves into Leti’s sequential 3D technology, leveraging FD-SOI and FinFETs, as well as other SOI-based monolithic 3D IC integration developments. A recommended read.

Posted January 13, 2014   -   Share this Buzz

Leti recently announced an agreement with Qualcomm Technologies, under which Qualcomm will assess the feasibility and the value of Leti’s sequential 3D technology. As opposed to 3D with TSVs, sequential 3D integration involves stacking active layers of transistors using molecular bonding. In his Electronics360 blog, Peter Clarke points out the synergies between the Leti process and FD-SOI.

Posted January 13, 2014   -   Share this Buzz

Simon Yang, the CEO of XMC, a fast growing specialty foundry in China, gave an excellent presentation about FD-SOI at the SOI Consortium’s Technology Summit in Shanghai (Oct., 2013).  The presentation is now available both through VLSI’s weSRCH site (click here) and through the SOI Consortium’s website (click here for this plus all the other Shanghai presentations).  While noting that over half of the world’s ICs are going into China, and three-quarters of them are <65nm, Yang’s looking at ways to boost his 12” utilization.

He asks if FD-SOI can be part of the solution, noting that it is a simple way to gain entry into fully-depleted technologies: it is a mature planar CMOS process, is easily portable for existing bulk designs, and is a particularly good choice for mobile markets.  Yang was formerly CTO of Chartered, which would indicate he’s familiar with SOI (pre-GloFo, Chartered produced PD-SOI chips for AMD).

While design houses in China want high performance and low power, they’ll go with whatever technology is good enough and cheap enough, he says. While he cites FD-SOI advantages, he also doesn’t pull any punches with respect to how he perceives the challenges, primarily with respect cost and ecosystem.

Posted January 13, 2014   -   Share this Buzz

eSIperformanceSoitec has issued a highly-informative new white paper on its enhanced signal integrity – aka eSI™ – wafers for 4G and LTE/A applications (to get the paper, click here).  Entitled “Innovative RF-SOI Wafers for Wireless Applications”, the paper explains the various challenges faced by RF IC designers, and how the new eSI wafers offer powerful solutions.  The substrates on which devices for LTE apps are manufactured play a major role in achieving requisite levels of performance.  They allow RF designers to integrate on the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies. As described recently in ASN (click here), the new eSI wafers are now in high-volume production, and are being used at most of the leading RF foundries.

Posted December 19, 2013   -   Share this Buzz

Advanced engineered substrate and materials leader Soitec and CEA-Leti, one of the world’s largest nanoelectronics labs, have signed a new five-year contract (press release here). This extends their partnership on engineered substrates and materials offering higher performance and energy savings at a competitive cost. The teams will teams will focus their efforts on developing new materials generations to support Soitec road maps in three markets: electronics, solar energy and lighting.

As Dr. Carlos Mazuré, CTO of Soitec, said,“In our industry, competitive pre-industrialization research, development of technology and product prototypes have become very important to make the difference. The CEA-Leti and Soitec partnership establishes a powerful alliance that is capable of answering the numerous challenges of today’s industrial requirements and building on our well-established material expertise.”

Laurent Malier, Director of CEA-Leti, said, “In recent years, Soitec has widely expanded its footprint and impact by addressing the electronics and energy challenges through its unique technologies which we developed together. Our partnership is the most efficient framework for securing research execution to support the ambitions of Soitec, and CEA-Leti teams are committed to its success.”

Soitec (founded in 1992) was originally a spin-off of Leti, where the company’s Smart Cut™ engineered wafer manufacturing technology was originally invented (in 1991).

Posted December 19, 2013   -   Share this Buzz

CEA-Leti announced that Leti-UTSOI2, the first complete compact model that enlarges the physically described bias range for designers, is available in all major SPICE simulators (press release here). Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. ST and Leti researchers presented UTSOI2 at IEDM 13. The model is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

“Enlarging the back biasing range accessible to the design community is key to optimizing the trade-off between performance and power consumption for UTBB technology,” said Thierry Poiroux, research engineer at Leti and model co-developer. “This provides more opportunities to utilize FDSOI’s advantages for mobile devices and other applications that require efficient energy use.”

The model’s development was supported by STMicroelectronics and partly funded by the ENIAC JU Places2Be project.

Posted December 19, 2013   -   Share this Buzz

Advanced substrate leader Soitec and Intelligent Epitaxy Technology, Inc. (IntelliEPI, Taiwan) a leader in InP, GaAs, and GaSb epi wafers, have signed a collaborative agreement to better serve the GaAs market (press release here).

“We are delighted to announce the license of our technology leading to a second source for our products for our key GaAs customers ,” said Bernard Aspar, Senior Vice President and Soitec’s Communication & Power Business Unit General Manager.

“This collaborative agreement will reinforce our GaAs technology and product know-how while, at the same time, offering Soitec’s customers supply-chain security,” said Yung-Chung Kao, IntelliEPI President and CEO.

Gallium arsenide (GaAs), a III-V semiconductor, is used in the manufacture of devices such as microwave frequency ICs, monolithic microwave ICs, infrared light-emitting diodes, laser diodes, solar cells and optical windows. GaAs is often used as a substrate material for the epitaxial growth of other III-V semiconductors including InGaAs and GaInNAs.

Posted December 16, 2013   -   Share this Buzz

EVG850LTlores

Equipment maker EVG announced that the Singapore-MIT Alliance for Research Technology (SMART) ordered an EVG®850LT fully automated production bonding system designed for SOI and direct wafer bonding using low-temp plasma activation processing (press release here). SMART researchers will use the system to support  advanced substrate development efforts.  According to Professor Eugene Fitzgerald from MIT’s Department of Materials Science and Engineering, SMART chose the EVG850LT for the center’s advanced R&D efforts due to the system’s high process flexibility and performance, EVG’s experience in low-temperature bonding, and expertise and support in process development.

Posted December 16, 2013   -   Share this Buzz

Concluding, “Faster, Simpler, Cooler,…and Cheaper: FD-SOI technology should get very good traction in the near future!”, semiwiki blogger Eric Esteve has kicked off a very lively conversation.  Within a few days of posting Faster, Cooler, Simpler, could FD-SOI be Cheaper too?, there were almost 20 comments, with lots of good supplemental information from well-informed participants. This must-read piece marks the latest in a series of high-profile semiwiki posts on FD-SOI.

Posted December 16, 2013   -   Share this Buzz

Two SOI pioneers have been elevated to the status of Fellow by the IEEE for their extraordinary accomplishents:

  • Jean-Pierre Raskin (Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium) – joined the “Class of 2014” for “contributions to the characterization of silicon-on-insulator RF MOSFETs and MEMS devices”.  Dr. Raskin received his PhD degree from UCL, where he is a professor and head of the Microwave Laboratory.
  • Carlos Mazure (Soitec, Bernin, France) – joined the “Class of 2013” for “leadership in the field of silicon on insulator and memory technologies”. Dr. Mazure is CTO of SOI wafer leader Soitec. He has filed more than 100 patents worldwide and is the author of 120 scientific papers. He holds two PhDs in physics, one from the University of Grenoble, France, and the other from the Technical University of Munich, Germany.
Posted December 5, 2013   -   Share this Buzz

Sand 9 has debuted the TM651, an SOI-based MEMS solution that it says achieves the stringent low-noise, high-stability and harsh environmental requirements for precision timing in communications infrastructure, industrial and military applications. It is the first product based on Sand 9’s patented Temperature Compensated MEMS Oscillator (TCMO™) platform.  Sand 9 is working closely with a number of leading analog semiconductor partners to provide reference designs for their synthesizer and timing products. Peter Real, vice president, High Speed Products and Technology, Analog Devices, commented: “As a leading supplier into communications infrastructure, industrial and military markets, Analog Devices is committed to exploring technologies that may improve the experience of our customers. Having initially invested in Sand 9 late last year, we are pleased to see them launch their first precision MEMS timing product.”

Posted December 5, 2013   -   Share this Buzz

Good news for the SOI ecosystem: SOI wafer suppliers Soitec and SunEdison (formerly MEMC) have ended their longstanding legal feud and entered into a patent cross-license agreement (press release here).  The agreement provides each company with access to the other’s patent portfolio for SOI technologies and ends all their outstanding legal disputes.

For Soitec, it represents a milestone for the SOI ecosystem, said Christophe Maleville, SVP of the company’s Digital Electronics Division.

For SunEdison, it adds to the company’s current SOI product capability, said Horacio Mendez, VP of the company’s Semiconductor Advanced Solutions division.

The agreement covers wafers for device architectures such as partially-depleted SOI (PD-SOI), fully-depleted SOI (FD-SOI) and radio-frequency SOI (RF-SOI) as well as advanced FinFETs.

The two companies have also agreed to grant each other the right to use their respective wholly-owned patents for research and development purposes. This applies to the development of products with advanced semiconductor materials beyond silicon that enable the fabrication of high-mobility channels for advanced generation digital applications.

Posted November 27, 2013   -   Share this Buzz

“At 14nm FD-SOI is much cheaper, 30-40% cheaper, than Intel’s technology,” Asen Asenov told David Manners in a recent Electronics Weekly post (see full post here).  Asenov is CEO and Founder of Gold Standard Simulations (GSS).  The subject of the post was how TSMC has turned to GSS for statistical analysis tools. Professor Asenov is a fan of ST’s FD-SOI, noted Manners. The main challenge is building the ecosystem, he concluded.

Posted November 27, 2013   -   Share this Buzz

D+R_ST_FDSOIslideDesign & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective.

After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk planar (28/20nm) and bulk FinFET (16/14nm).  He then gives examples of ARM core IP, and how FD-SOI is leveraged in ultra-low-voltage, analog and high-speed apps.

Posted November 18, 2013   -   Share this Buzz