Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
Under a new agreement, Simgui now has the exclusive right to promote, distribute and sell Soitec’s 200-mm SOI wafers in China (see press release in English here; Chinese version here). Soitec is the world’s leading producer of SOI wafers. Shanghai Simgui Technology Co., Ltd. (Simgui), a Shanghai-based semiconductor materials company, is a spinoff of the Shanghai Institute of Microsystem and Information Technology (SIMIT/CAS).
Available in different product families, the 200mm SOI wafers are used in chips such as RF ICs broadly used in smartphones and power ICs for automotive applications. This agreement, which follows a previous licensing and manufacturing partnership between the two companies, represents another key step in establishing a Chinese SOI ecosystem while also strengthening Soitec’s presence in this double-digit-growth semiconductor market.Posted December 9, 2014 - Share this Buzz
Two new products from semi equipment manufacturer Altatech: one for ultra-thin film deposition, and one for searching out nano-defects. Altatech is a division of Soitec, best known in the advanced substrates community for its leadership in SOI wafers. This part of the company, however, develops highly efficient, cost-effective inspection and chemical vapor deposition (CVD) technologies used for R&D and manufacturing of semiconductors, LEDs, MEMS and photovoltaic devices.
The company’s newest inspection system, the Orion Lightspeed™, is capable of pinpointing the size and location of nano-scale defects inside compound semiconductor materials and transparent substrates (see press release here). The new system helps to ensure the quality control of high-value engineered substrates used in several fast growing markets including high-brightness LEDs, power semiconductors and 3D ICs. Inspection is based on Altatech’s patented synchronous Doppler detection™ technology, which determines the exact size and position of defects by making direct physical measurements with resolution below 100 nm. This provides true defect sizing, as opposed to other types of inspection equipment on the market that make indirect measurements using diffracted light to calculate approximate defect sizes. It handles 200mm or 300mm substrates, with throughput of 85 and 80 wafers per hour, respectively. Beta systems have already been installed at customers’ facilities and are demonstrating excellent performance. Shipments of production units are scheduled to begin in April 2015.
The new AltaCVD 3D Memory Cell™ is the latest member of Altatech’s AltaCVD line, designed to deposit ultra-thin semiconductor films that enable the manufacturing of high-density, low-power memory ICs used throughout mobile electronics (see press release here). The new system performs atomic-layer deposition 10 times faster than conventional atomic-layer deposition (ALD) systems, helping to meet global market demands for both high-volume production and cost efficiency in fabricating advanced memories. The system is currently demonstrating its unique capabilities and performance at one of Altatech’s key customers. Production units are available.Posted December 8, 2014 - Share this Buzz
SOI-MEMS timing device leader SiTime Corporation is being acquired by MegaChips Corporation, a top 25 fabless semiconductor company based in Japan for $200 million in cash. (read the press release here). This transaction combines two complementary fabless semiconductor leaders that provide solutions for the growing Wearables, Mobile and Internet of Things markets.
“MEMS components are fuelling the growth of the semiconductor industry, “said Akira Takata, President and CEO of MegaChips Corporation. “Through the acquisition of SiTime, MegaChips becomes a leader in MEMS. SiTime will help us expand our portfolio and diversify our customer base. SiTime technology is the perfect match for MegaChips’ solutions that target Wearables, Mobile and IoT markets.”
SiTime’s innovative SOI-MEMS timing solutions replace dated quartz products in the telecom, networking, computing, storage and consumer markets, with the benefits of higher performance, smaller size, and lower power and cost. ASN has been following SiTime for over five years, since they first spun off of Bosch, and CTO Markus Lutz explained the role SOI plays in their technology (which you can read here). You can also read more about SiTime products and technology here by clicking the ASN SiTime tag.
SiTime will retain its name and operate as a wholly owned subsidiary of MegaChips.
Posted November 3, 2014 - Share this Buzz
Soitec, a leader in SOI wafers and other advanced substrates, recently announced the sale of its gallium arsenide (GaAs) epitaxy business (the Soitec Specialty Electronics subsidiary) to Intelligent Epitaxy Technology Inc (see press release here). The deal follows the previous collaboration between Soitec and IntelliEPI (see press release dated December 12, 2013).
“The sale of our gallium arsenide (GaAs) epitaxy business to IntelliEPI reflects our drive to refocus Soitec’s electronics division on its key products under its five-year Soitec 2015 program,” explained Bernard Aspar, Senior Vice President and Soitec’s Communication & Power Business Unit General Manager.
“The transaction will enable IntelliEPI to widen its customer base and penetrate to several critical GaAs application markets such as automotive radar technology. It will also enable IntelliEPI to provide best-valued products and services to all its customers with expanded manufacturing capacities from its Texas, USA location,” said Yung-Chung Kao, IntelliEPI President and CEO.
Posted November 3, 2014 - Share this Buzz
Peregrine Semi senior marketing manager Kinana Hussain says the company’s new RF-SOI PE42722 switch “…is a game changer for the cable industry,” (see press release here). The UltraCMOS® PE42722 is a high-linearity RF switch that enables a dual upstream/downstream band architecture in cable customer premises equipment (CPE) devices. “By enabling a dual-band architecture, customers will be able to make a simple phone call to their cable service provider, who can then, ‘with the flip of a switch’, upgrade their customer’s high-speed data service plan. The added bonus of also complying with the DOCSIS 3.1 standard makes this switch a must-have for all next-generation CPE devices,” he concludes.Posted October 27, 2014 - Share this Buzz
In a piece entitled Time To Look At SOI Again (you can read it here), SemiconductorEngineering Executive Editor Mark Lapedus charts the industry’s accelerating interest in SOI, including FD-SOI and FinFETs on SOI.
He notes that FD-SOI is now planned for four generations: 28nm, 20nm, 14nm and 10nm. The offering has expanded beyond ST to Samsung and GF. He quotes GF’s Mike Mendicino as saying, “We’re seeing a lot of interest from customers (for FDSOI).”
For FinFETs, he quotes Terry Hook’s IBM presentation at the recent IEEE S3S Conference, when he said that on SOI, “…the formation of the fin is blindingly simple”. (If you missed Terry’s ASN piece last year, you can read it here.)Posted October 27, 2014 - Share this Buzz
In a blog entitled “FD-SOI Will Be Mainstream” (8 October 2014 – read it here), ElectronicsWeekly’s David Manners reports that the CEO of Synapse Design predicts FD-SOI will be a mainstream technology.
Synapse has been working in FD-SOI since 2011, has already taped out three designs and has more in the pipeline, the CEO told Manners. He sees a lot of activity coming from Japan and China in automotive and mobile as well as in network infrastructure.Posted October 17, 2014 - Share this Buzz
SOI wafer leader Soitec was awarded the Best Partnership Award by Sony Semiconductor. Soitec earned the recognition for outstanding support that has contributed to Sony’s success in the RF semiconductor market.
Soitec’s high-resistivity silicon-on-insulator (HR-SOI) wafers have long been a favorite of RF designers for 2G and 3G switches. But the company’s latest eSi substrates has taken off like wildfire, and are now used by all the major companies that make RF chips for smart phones. The eSI wafers enable much higher linearity and isolation, helping designers to address some of the most advanced LTE requirements at competitive costs. You can read more about the technical details of the wafers and how they were developed here and how they solve key challenges here.
“We are very honored to receive this award from Sony recognizing the long partnership between our companies,” said Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit. “It demonstrates Soitec’s commitment to deliver the enabling substrates that support Sony’s RF devices business.”Posted October 17, 2014 - Share this Buzz
All the presentations made at the SOI Consortium‘s Shanghai workshops on RF-SOI and FD-SOI are now being posted.
The RF-SOI posting includes presentations from IBS, ST, UCL, Skyworks, Shanghai Technology Institute, IBM, SMIC, Soitec and GlobalFoundries – click here for those.
The FD-SOI postings include presentations from IBS, ST, Synopsys, Verisilicon, Wave Semi, IBM and GlobalFoundries – click here for those.
As of this writing, most of the presentations are available – the rest will follow very shortly so check back soon if the one you want is not there yet.
Posted September 26, 2014 - Share this Buzz
“ST needed a fast, practical method to ensure our IP would not be susceptible to noise issues, when implemented in complex, multi-million gate SoCs. We have also found we can optimize the power-supply requirements to IP in the knowledge that both the position and number of pins or bumps will be adequate for the IP as implemented,” said Pierre Dautriche, Physical IP & Mixed Design Solutions Director, Central CAD & Design Solutions, STMicroelectronics. “Extensive use here has proven WaveIntegrity as the most efficient and effective way to achieve these aims, allowing us to reduce risk in ways previously impossible. This capability is being extended to both our most advanced and older process nodes, and which we will also support for our own customers. ”
ST is using WaveIntegrity across groups designing complex IP for home and automotive devices. Getting a fast, initial picture of potential noise-related issues is vital in designing today’s complex SOCs and WaveIntegrity performs noise-analysis results right from the initial floorplan, as IP is delivered to the chip assembly team.
WaveIntegrity encourages noise-analysis results to be used during the first and subsequent floorplan stages, so that critical design decisions can be made early and at low cost. The analysis setup is then refined for the final floorplan revision to support any potential remaining noise-related design choices before final place & route.Posted September 26, 2014 - Share this Buzz
Revelations by semiwiki’s Eric Esteve that TSMC has filed a significant FD-SOI patent has generated a rush of speculation in the press and online forums. In his piece When TSMC advocates FD-SOI…, Esteve noted that TSMC’s patent for “Planar compatible FDSOI Design Architecture” (granted 14 May 2013) heralded the advantages as follows: “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.”
In a subsequent article in Electronics Weekly entitled TSMC Developing FD-SOI, David Manners concluded, “Clearly all mobile IC houses are looking at FD-SOI as an option because of its lower power potential. The fact that TSMC is developing the technology suggests that a customer or customers have enquired about using FD-SOI…”.Posted September 17, 2014 - Share this Buzz
RF-SOI Pioneer Peregrine has announced new switches for wireless infrastructure and carrier-grade WiFi. The UltraCMOS® PE42442 and PE42452 high-isolation, multi-throw switches address emerging requirements in wireless infrastructure equipment (read press release here). The UltraCMOS® PE42424 RF Switch enables 802.11ac Wi-Fi access points to deliver faster data rates in high-density, bring-your-own-device environments, with 60 percent power handling increase and 75 percent smaller footprint (read press release here)
In his recent piece, A couple of misconceptions about FD-SOI (3 September 2014), semiwiki blogger and IP expert Eric Esteve corrects some assertions surfacing about FD-SOI. He reminds designers that to really benefit from FD-SOI, you want to leverage body-biasing. He explains how ST has automated the IP conversion process so it takes about half the time you’d normally expect. He also advocates FD-SOI for wearables and smartphones, as it provides both performance advantages and power savings.Posted September 11, 2014 - Share this Buzz
A thoroughly engaging and amusing LinkedIn Pulse piece by Bruce Kleinman comes down firmly on the side of 28nm FD-SOI. Entitled 28nm: Home Improvements (posted 13 August 2014), it’s subtitled, “Welcome to 28nm! Make yourself comfortable, we’re going to be here for awhile.” He says (among lots of other things, including astute observations about 3D), “…in my book 28nm FD-SOI offers very similar performance/power characteristics to 20nm bulk silicon.” Kleinman’s currently SVP at HMicro, which is doing SOC solutions for demanding wireless apps and IoT. He’s clearly got the street creds, arriving there by way of upper management at GlobalFoundries, Xilinx, HP, etc., having started out with a Stanford MSEE. A good read – recommended.Posted September 11, 2014 - Share this Buzz
An excellent article in SST details Leti’s monolithic 3D (M3D) technology, as presented at the SemiconWest 2014 Leti Day (read the full article here). Written by Brian Cronquest, MonolithIC 3D’s VP Technology & IP, the piece covers a presentation given by Olivier Faynot, Leti’s Device Department Director, about “monolithic 3D technology as the ‘solution for scaling’.” Cronquest puts the big picture in perspective, while providing plenty of technical information. He ends by reminding readers that this and other key work will be further detailed at the IEEE S3S Conference (S3S = SOI + 3D + Subthreshold Microelectronics) October 6-9, 2014 at the Westin San Francisco Airport (see the conference website here).Posted September 1, 2014 - Share this Buzz