Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
A new book entitled Silicon-On-Insulator (SOI) Technology, Manufacture and Applications (1st Edition) features contributions by experts at Soitec, GF, TSMC, Leti and more.
Billed as “a complete review of this rapidly growing high-speed, low-power semiconductor technology,” the book covers the entire SOI spectrum, from Moore to More than Moore. It goes into SOI wafer technology, electrical properties, modeling, PD-SOI, FD-SOI, FinFETs and junctionless transistors, RF, ultralow-power, photonics, memory, power and MEMS. (See Table of Contents here.) This book should be a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics, as well as for electrical engineers in the automotive and consumer electronics sectors.
Silicon-On-Insulator (SOI) Technology, Manufacture and Applications is published by Woodhead Publishing, and is also available in print and ebook forms from major online retailers such as Amazon, Elsevier and Barnes & Noble. It was compiled and edited by Oleg Kononchuk, chief scientist at Soitec, France, and Bich-Yen Nguyen, a senior fellow at Soitec, USA.Posted August 8, 2014 - Share this Buzz
Soitec estimates that it has shipped enough of its eSI wafers to fabricate more than 1.4 billion RF front-end semiconductor devices. (Read the press release here.) The proprietary Enhanced Signal Integrity™ (eSI) substrates are now the substrate of choice for manufacturing cost-effective and high-performance radio-frequency (RF) devices providing a power boost for 4G /LTE applications.
For eSI, Soitec and the Université catholique de Louvain (UCL) developed a technique that adds a “trap-rich” layer underneath the buried oxide, which freezes the parasitic surface conduction that’s inherent in any oxidized silicon substrate. (The technical details are clearly explained in an excellent ASN post by the Soitec and UCL team leaders – click here to read it.) Using a set of very specific patents, Soitec applied proprietary technology and accumulated knowledge to build the new eSI product line.
This substrate provides a raft of advantages to RF design. Because the trap-rich layer is built into the substrate, it reduces the number of process steps and relaxes design rules, leading to a highly competitive performance and die cost, including a smaller area per function. RF designers can therefore integrate diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss, better thermal conductivity and better signal integrity than other technologies. (Click here to read Soitec’s ASN post from December 2013 describing all the RF design challenges eSI answers.)Posted July 18, 2014 - Share this Buzz
ST has posted a series of helpful website page for those new to FD-SOI – click here to see it. It starts with the basics, moves onto a discussion of how FD-SOI continues Moore’s Law, and finishes with info on power efficiency, memories, analog and high-speed designs.Posted July 15, 2014 - Share this Buzz
An excellent article highlighting Leti’s work on monolithic 3D was recently published in the IEEE’s Spectrum magazine – click here to read it. In the article, Maud Vinet, manager of advanced CMOS at Leti says they’ve worked closely with ST to ensure manufacturability. “There is no major roadblock to the transfer of this technology to foundries,” she says in the article. “I feel very confident when I say that.” In case you missed it, leaders of Leti’s 3D team also published a very informative piece right here in ASN – click here to read it.Posted July 15, 2014 - Share this Buzz
Specialty foundry TowerJazz announced the availability of an enhanced RF-SOI CMOS process design kit (PDK) for its 0.18µm process technology (see press release here). The kit was developed for use with Agilent Technologies’ Advanced Design System (ADS) software and targets a wide range of analog markets including front-end modules for mobile phones, tablets and WiFi terminals.Posted June 17, 2014 - Share this Buzz
A ppt presentation by STMicroelectronics entitled Features and Benefits of 14nm UTBB* FD-SOI Technology is now posted on WeSRCH (click here to view it). It is fairly technical, covering process boosters, modules and innovations, mask sequences, performance and scalability.Posted June 17, 2014 - Share this Buzz
IBM Foundry Solutions announced a new SOI-based technology for RF called 7SW SOI. The company says it is designed for 30 percent better performance than its predecessor, 7RF SOI, with which IBM shipped over seven billion chips in the last three years. The new mobile phone chip technology can help device manufacturers provide consumers with extremely fast downloads, higher quality connections, and longer battery life than its highly successful predecessor, says an IBM spokesperson. The new technology is designed to take advantage of more frequency bands, taking phone manufacturers one step closer to the reality of creating a “world phone” that can be used anywhere.
Here are the key points:
- The new technology gives designers added flexibility, enabling them to develop chips that integrate more function or that take up to 30 percent less space, depending on design goals.
- The new technology is a hybrid 180nm/130nm technology base and devices optimized to accommodate aggressive LTE standards and demanding worldwide coverage requirements
- It is optimized for multi-band switching in next-generation smartphones.
- Poised to drive innovation in newer category of smart devices in the Internet of Things as the new technology is an ideal fit for high-band LTE and Wi-Fi 5.8 GHz band applications.
- Clients can exploit the technology advances offered by 7SW to develop solutions that enhance user experiences, including broader geographic mobility and faster data rates for high definition video.
For a helpful brochure on IBM’s RF foundry offerings, click here.Posted June 17, 2014 - Share this Buzz
SiTime, which leverages SOI for high-performance MEMS timing solutions, has introduced what it says is the smallest, lowest power 32 kHz TCXO (temperature compensated oscillator – read the press release here). With its tiny footprint and ultra-low power consumption, the SiT1552 MEMS TCXO enables a paradigm shift in the size and battery life of wearable electronics and Internet of Things (IoT); such benefits are not available from legacy quartz devices.
“The SiT1552 MEMS TCXO is 20% of the size and consumes 50% of the power of comparable quartz devices,” said Piyush Sevalia, executive vice president of marketing at SiTime. “Our MEMS enable new system architectures that offer higher performance, small size and longer battery life. With another industry first, we continue to revolutionize the timing industry with our breakthrough MEMS solutions.”
Devices are in production now. Pricing is available upon request.Posted June 8, 2014 - Share this Buzz
Soitec, the world leader in SOI wafer manufacturing, has hired a former Intel exec, Thom Degnan, to take on the job of VP of the company’s sales and bizdev for the Electronics Division in North America (read press release here). Soitec says that this strategic hiring supports the Electronics Division’s focus on mobile markets with FD-SOI wafers for digital electronics and RF-SOI wafers for RF applications.
His experience is clearly right in the sweet spot for Soitec. Prior to joining the company, Degan was vice president of business development for Intel’s Services Division and, prior to that, vice president and general manager of the Americas Region of Intel Mobile Communications. Previously he was vice president and general manager of the Americas Region of Infineon Technologies, Inc., where he was responsible for all sales, business development and marketing for the company’s Communications Division, which Intel acquired in 2011.
Degnan will be based in San Diego, California.Posted June 8, 2014 - Share this Buzz
In an EETimes blog, Handel Jones of IBS says that the Samsung-ST FD-SOI announcement represents a major opportunity. (Read full blog here.) “Samsung Electronics has a major opportunity with its large wafer capacity to support low-leakage products with its 28 nm FD-SOI process,” he wrote. “Cadence Design Systems, Synopsys, and Mentor Graphics are all supporting the FD-SOI ecosystem, and the transition from 28 nm bulk HKMG to FD-SOI should be inexpensive.” He goes on to say, “It is also important to be able to transition the smartphone vendor base to China and meet the aggressive pricing structures of the China market, which can be done with FD-SOI. Adopting FD-SOI gives a high probability of having a cost-competitive and low-power option for high-volume mobile platforms.”Posted May 28, 2014 - Share this Buzz
Peregrine Semi has shipped the first RF switches built on the company’s SOI-based UltraCMOS 10 technology platform. With partner GlobalFoundries, Peregrine also announces the completion of product and process qualification for the advanced RF-SOI technology (see press release here). The 130 nm technology combines the performance of UltraCMOS technology with the economies of SOI, and it delivers a more than 50-percent performance improvement over comparable solutions, says Peregrine. It targets the unique growth requirements for mobile applications and is the foundation for Peregrine’s next- generation RF switches, tuners and power amplifiers, including the industry’s first reconfigurable RF front end, UltraCMOS Global 1.Posted May 28, 2014 - Share this Buzz
Soitec and Simgui (Shanghai, China) are partnering on SOI wafer production for RF and power applications. The newly signed deal (read press release here) includes a licensing and technology transfer agreement. Simgui will establish a high-volume SOI manufacturing line using Soitec’s proprietary Smart Cut™ technology to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide. Beyond this initial cooperation, the two companies plan to expand their collaborative efforts in the future to take advantage of their synergies.Posted May 28, 2014 - Share this Buzz
Within 24 hours of the news that Samsung was the new foundry for ST’s 28nm FD-SOI, the news made headlines across all the major tech pubs and social media forums. EETimes, Electronics Weekly, ZDNet and more are all resolutely enthusiastic about the deal. SemiWiki founder Dan Nenni said it was “…one of the biggest stories we will cover this month, if not this year, absolutely.” And David Manners quipped that it’s “Game On For FD-SOI”. On Twitter, close to 500 tweets about the news were posted within the first 24 hours from all corners of the globe, and in at least a dozen languages. Not Lady Gaga, perhaps, but huge by tech standards nonetheless. Even Samsung got into the act, with Senior Director Foundry Marketing Kelvin Low blogging that, “This particular version of FD-SOI delivers a nice balance of higher performance with low power and is well suited for mobile and consumer electronics to IT infrastructure applications.”Posted May 19, 2014 - Share this Buzz
The FD-SOI announcement by Samsung and ST represents a tipping point for FD-SOI deployment and for Soitec’s electronics business in the next decade (see Soitec press release here), says the company whose substrate technology makes it all possible. Soitec is the world leader in SOI wafer manufacturing. This announcement validates Soitec’s early strategic technology choice to develop the starting wafers used as a foundation for FD-SOI chip manufacturing. Working in partnership with Leti and ST, Soitec’ s R&D efforts have been focused on ultra-thin product generation for most of the past decade.Posted May 19, 2014 - Share this Buzz
Cadence has announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics. (See Cadence press release here.) On this new process node, the Cadence® Denali™ DDR4 IP supports up to 2667Mbps performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to quickly take advantage of the DDR4 standard. In addition, the ultra-low-power Cadence USB High-Speed Inter-Chip (HSIC) PHY IP is also available on this process, which the company says is an ideal solution for inter-chip USB applications. Cadence also announced the qualification of its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI processPosted May 19, 2014 - Share this Buzz