Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.


Within 24 hours of the news that Samsung was the new foundry for ST’s 28nm FD-SOI, the news made headlines across all the major tech pubs and social media forums. EETimes, Electronics Weekly, ZDNet and more are all resolutely enthusiastic about the deal. SemiWiki founder Dan Nenni said it was “…one of the biggest stories we will cover this month, if not this year, absolutely.” And David Manners quipped that it’s “Game On For FD-SOI”. On Twitter, close to 500 tweets about the news were posted within the first 24 hours from all corners of the globe, and in at least a dozen languages. Not Lady Gaga, perhaps, but huge by tech standards nonetheless.  Even Samsung got into the act, with Senior Director Foundry Marketing Kelvin Low blogging that, “This particular version of FD-SOI delivers a nice balance of higher performance with low power and is well suited for mobile and consumer electronics to IT infrastructure applications.”

Posted May 19, 2014   -   Share this Buzz

The FD-SOI announcement by Samsung and ST represents a tipping point for FD-SOI deployment and for Soitec’s electronics business in the next decade (see Soitec press release here), says the company whose substrate technology makes it all possible. Soitec is the world leader in SOI wafer manufacturing. This announcement validates Soitec’s early strategic technology choice to develop the starting wafers used as a foundation for FD-SOI chip manufacturing.   Working in partnership with Leti and ST, Soitec’ s R&D efforts have been focused on ultra-thin product generation for most of the past decade.

Posted May 19, 2014   -   Share this Buzz

Cadence has announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics. (See Cadence press release here.) On this new process node, the Cadence® Denali™ DDR4 IP supports up to 2667Mbps performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to quickly take advantage of the DDR4 standard. In addition, the ultra-low-power Cadence USB High-Speed Inter-Chip (HSIC) PHY IP is also available on this process, which the company says is an ideal solution for inter-chip USB applications. Cadence also announced the qualification of its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process

Posted May 19, 2014   -   Share this Buzz

SoitecRFSOIwafersA Soitec white paper entitled Innovative RF-SOI Wafers for Wireless Applications is now available on the weSRCH website (see paper here). The paper explains the value of using RF-SOI substrates, and what the latest generation of Soitec’s WaveSOI™ and eSI™ wafers brings to RF IC performance. It also explains how these substrates simplify the IC manufacturing process in order to address the mainstream smartphone market.

Posted May 7, 2014   -   Share this Buzz

Kalray is considering an FD-SOI version of its family of programmable multicore processors, reports Peter Clarke of Electronics360 (see article here).  Clarke says that Kalray’s director of solutions and software services told him that while they’re currently on 28nm bulk, they’ve had customer interest in an FD-SOI version of a planned 64-core chip for telecom, automotive and medical apps.  The company says that its gigaflops-per-watt ratio is already one of the world’s best, and an FD-SOI version would make it even better.

Posted May 7, 2014   -   Share this Buzz

FraunhoferSOIhitemp2Fraunhofer scientists have developed a new type of high-temperature SOI-based process for making extremely compact chips that withstand temperatures of up to 300 degrees Celsius (press release here).  At a characteristic dimension of 0.35 µm, they are considerably smaller than the high-temperature chips available today, they say.  Targets include oil production and geothermal power applications. “It becomes possible with this process to fabricate extremely compact microchips that operate flawlessly even at temperatures of up to 300 degrees Celsius,” said Holger Kappert, head of High-Temperature Electronics at Fraunhofer IMS.

Posted May 7, 2014   -   Share this Buzz

100K views and counting: FD-SOI-related posts on SemiWiki are fabulously popular. Following a wrap-up by Paul McLellen of his FD-SOI talk at EDPS (read post here), heated discussion ensued in the comments section.  To show just how hot a topic FD-SOI is in the design community, SemiWiki co-founder Dan Nenni shared the following stats:

  • 100,000 FD-SOI article views on SemiWiki
  • Top referring domain is intel.com
  • Top geographic regions are North America, Taiwan, Korea
  • 160 FD-SOI blog comments
  • Top Google searches: FD-SOI Wiki, FD-SOI vs FinFET

Clearly, FD-SOI is a hot topic!

Posted April 30, 2014   -   Share this Buzz

ST has signed a new foundry for 28nm FD-SOI manufacturing, but isn’t yet saying who it is.

In a press release issued with the STMicroelectronics’ 2014 First Quarter Financial Results (read press release here), Jean-Marc Chery, Executive Vice President and General Manager, Embedded Processing Solutions, said, “We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assures the industry of high-volume production of ST’s FD-SOI based IC solutions for faster, cooler, and simpler devices and strengthens the business and financial prospects of the Embedded Processing Solutions Segment.”

During the subsequent call with analysts (transcript on Seeking Alpha here), CEO Carlo Bozotti added that, “ST’s unique FD-SOI technology is well on its way to become a significant revenue generator for 2015 and beyond….”

Posted April 30, 2014   -   Share this Buzz

To date, over 40 readers have commented on Handel Jones’ (IBS) EETimes post entitled FinFETs Not the Best Silicon Road (read post here).  He noted that, “…next-generation 20nm bulk high-K metal gate CMOS and 16/14nm FinFET process will deliver smaller transistors. However, they will also have a higher cost per gate than today’s 28nm bulk HKMG CMOS…”.  He then went on to say, “One option […] is fully depleted silicon-on-insulator (FD SOI). It gives lower cost per gate and lower leakage than bulk CMOS and FinFETs.”

Posted April 30, 2014   -   Share this Buzz

Synopsys has announced that STMicroelectronics has standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization.  As noted in the press release (read here) ST has a unique processor architecture made possible through their FD-SOI process technology.  An FD-SOI device can operate at significantly higher frequencies than an equivalent, traditional, bulk CMOS device. It can also run very fast at low voltages, providing much higher energy efficiency. The close collaboration between the ST design teams and Synopsys has led to a compelling implementation solution that fully exploits the performance and power promise of FD-SOI technology and provides the throughput needed to meet tight time to market windows.

Posted April 25, 2014   -   Share this Buzz

A team from King Abdullah University of Science and Technology (Saudi Arabia) has published an article in Advanced Materials (22 February 2014) entitled Flexible and Transparent Silicon-on-Polymer Based Sub-20 nm Non-planar 3D FinFET for Brain-Architecture Inspired Computation. As subsequently described in an article in Nanowerk (article here), “…the team demonstrates a pragmatic approach to transforming silicon-on-insulator (SOI) based state-of-the-art FinFET into flexible and semi-transparent silicon-on-polymer FinFET while retaining high performance and integration density.” This marks the industry’s first FinFET layer transfer, team member Dr. Muhammad Mustafa Hussain told ASN.

DOI: 10

Reproduced with permission

An industry standard 8′′ SOI wafer based ultra‐thin (1 μm), ultra‐light‐weight, fully flexible and remarkably transparent state‐of‐the‐art non‐planar three dimensional (3D) FinFET is shown. It has sub‐20 nm features and the highest performance ever reported for a flexible transistor. (Courtesy: WILEY-VCH Verlag GmbH, Advanced Materials and King Abdullah University of Science and Technology. Reprinted with permission.)

Posted April 25, 2014   -   Share this Buzz

Altatech, a subsidiary of Soitec, has received an order for its Orion LedMax wafer inspection and metrology system from OSRAM Opto Semiconductors GmbH, one of the world’s leading manufacturers of opto electronic components (read press release here). OSRAM will use the tool to improve the performance, cost efficiency and yield of its LED-processing operations. The leading-edge inspection system, suitable for both volume manufacturing and R&D applications, will perform production control and new product qualification of OSRAM’s epitaxial wafers used in fabricating LEDs.

Best known to many as the world leader in SOI wafer manufacturing, Soitec’s other divisions are also leaders in their areas, with wafer manufacturing equipment and products related to LEDs and solar (CPV) technology.

Posted April 25, 2014   -   Share this Buzz

After a very successful first edition in 2013, the 2014 IEEE S3S will take place in San Francisco, 6-9 October, 2014 (click here for details). IEEE S3S combines the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, and adds a parallel track in 3D Integration. The technical sessions will be preceded by two one-day Tutorial Short Courses. Fundamental Classes are also offered. The Call for Papers submission deadline has been set for 5 May 2014 (click here for more info).

Posted April 9, 2014   -   Share this Buzz

Sans titre

The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates matching those of more conventional CVD techniques. The system will be used by both internal and external researchers in fabricating a broad range of semiconductor-based devices including leading-edge CMOS transistors, MEMS, ICs built with the latest in through-silicon-via (TSV) technology, advanced LEDs and solar cells. Altatech is a subsidiary of Soitec (the world leader in SOI wafer manufacturing). AltaCVD systems have been used extensively in R&D and pilot production facilities throughout Europe; however, the University of Washington’s order represents the first such system to be delivered to a North American university R&D and pilot production facility.

Dr. Michael Khbeis, acting director of the WNF, said, “The AltaCVD system provides a unique capability that enables researchers to deposit conformal metal films for TSV applications as well as metal oxides and nitrides for high-k dielectrics and piezoelectric materials. The higher deposition rate enabled by pulsed CVD makes ALD films a tractable solution for scale-up paths toward high-volume manufacturing for our researchers and industrial clients. This ensures a viable pathway from academia to real economic impact in our region.”

Posted April 9, 2014   -   Share this Buzz

Tronics_SOI_MEMS      Leti_NMEMS_Ultimes_V2

A year after announcing the industrialization of CEA-Leti’s breakthrough M&NEMS technologies, Tronics has successfully designed and manufactured the first batch of six-degrees-of-freedom (6DOF) MEMS chips, with 3 accelerometers and 3 gyroscopes on a single die (press release here). Built on SOI wafers, with a die size of less than 4mm2, this 6DOF MEMS chip is one of the smallest in the industry, and Tronics says further optimization will make it the smallest. Besides its size advantage, the piezoresistive nanowire based technology significantly decreases power consumption and allows manufacturing of all sensor types (accelerometers, gyroscopes, magnetometers, pressure sensor and microphone) using a common process flow.

This first functional batch is an important milestone towards high volume production. The industrialization work will continue through 2014, with the first commercial samples available in Q4 2014. An ASIC is also being designed and will be available in 2014 to complete the sensor platform. In addition to the 6DOF device, Tronics has also designed a very compact 9DOF monolithic MEMS. Samples will be available by the end of this year.

Target applications for this new generation of inertial devices are those where size and/or power are key: wearable devices, smartphones and tablets.

Posted April 9, 2014   -   Share this Buzz