Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
A powerful, detailed article in EETimes-Asia details how FD-SOI Supports Moore’s Law (click here to read it). Written by Laurent Remont, ST’s VP and GM for Technology and Product Strategy, Embedded Processing Solutions, it explores FD-SOI’s advantages in terms of price, power and performance versus planar bulk CMOS and FinFETs and 28nm and 14nm.
Remont explains how structurally it is the most cost-effective sub-30nm process technology because FD-SOI is much simpler. In an interesting twist, he goes on to describe how forward body biasing (FBB) allows for dynamic power / leakage / frequency tuning linked to datacenter load. “With this, energy use would be proportional to workload and FD-SOI could reduce global data center power by up to 50 per cent,” he says.
In terms of performance, he says, “…the switch from 28nm Bulk CMOS to 28nm FD-SOI can improve circuit speed by as much as 35%. Even with this performance, FD-SOI transistors run cooler, because of lower leakage, wider voltage scaling and FBB all leading to higher power efficiency.
He concludes that FD-SOI will enable the industry to validate Moore’s Law down to 10nm. A highly recommended read.
Soitec Sr. VP (and FD-SOI wafer guru) Christophe Maleville has written a very good, high-level piece in the Global Semiconductor Alliance (GSA) Forum. Entitled Technology Selection Implications Intensify and Options are Limited, the piece examines cost-per-gate trends and explores roadmap options. He shows how FD-SOI provides a path forward with continued scalability, significant cost advantage and execution risk reduction vs. all other options. (Read the article here – GSA membership not required.)
Posted February 28, 2014 - Share this Buzz
Semiwiki blogger Paul McLellan has written an excellent piece on the FD-SOI analog-to-digital converter (ADC) that ST presented recently at ISSCC. (Read the article here.) He notes, “This is a very high performance ADC and thus an example of complex high-precision analog design in FD-SOI.” He concludes, “Together with the low-power capability of the 28nm CMOS UTBB FDSOI technology, ST could reach 10GS/s operation while keeping the power consumption at 32mW under 1V supply with a block that is just 0.009mm2.” Recommended technical read.
Posted February 28, 2014 - Share this Buzz
Altatech, a CVD/equipment subsidiary of SOI wafer leader Soitec, announced a new collaborative partnership to research and develop materials for the next generation of high-efficiency solar cells. Joining forces with Helmholtz-Zentrum Berlin für Materialien und Energie (HZB), a member of the Helmholtz Association of German Research Centres, Altatech will be working on new classes of materials and innovative device structures for photovoltaic and photocatalysis applications. Altatech will install a new single-substrate multi-chamber solution (an AltaCVD system) at HZB’s newly constructed Energy Materials In-situ Laboratory (EMIL) at the synchrotron light source BESSY II facility in Berlin. (Read press release here.)Posted February 28, 2014 - Share this Buzz
(Courtesy: Synopsys, STMicroelectronics, ARM)
An excellent ARM TechCon 2013 video on FD-SOI for designers is now posted on the Synopsys site. David Jacquet from ST shares the company’s FD-SOI approach to delivering optimized energy efficient solutions for the SoC market. Jacquet currently leads ST’s architecture activities for energy efficient high performance CPU/GPU implementations. In his presentation (click here to view it) entitled, “Energy Efficient Implementation of ARM® Cortex©-A57/-A53 Processor Cores in FD-SOI Process Technology”, he begins with with an overview of the FD-SOI process technology as an enabler for high performance / low power design. Highlights from the low power implementation and verification methodology developed with Synopsys, including results and best practices, are also presented. This is a technical presentation, covering ST’s process technology and ARM-core based SoC product roadmap. ARM TechCon is ranked one of the top three must-attend events in the embedded industry. Highly recommended viewing.Posted February 20, 2014 - Share this Buzz
Citing SOI in the Power family of high-performance processors, Chipworks concludes that IBM is a major source of chip innovation. In a recent EETimes article (read it here), which charts IBM developments at the transistor level over the last decade, the article notes that “..the 32 nm technology used to fabricate the IBM Power7+ represents an extraordinary technical achievement. IBM continues to be one of the technology leaders in the global semiconductor industry.” The article has excellent charts and pictures, and is a recommended read for anyone interested in the evolution of leading-edge SOI-based processors over the last decade.Posted February 20, 2014 - Share this Buzz
“High performing low power digital technology based on SOI” is an important part of the detailed plan submitted February 14th by the Electronics Leaders’ Group (ELG) to European Commission Vice-President Neelie Kroes. (Press release here.) The group recommends the EU focus on:
- Areas were Europe is strong – automotive, energy, industrial automation and security. The target is to double current production in the next 10 years.
- New high growth areas, in particular Internet of Things (IoT) and the development of ‘Smart-X’ markets (e.g. smart homes, smart grids etc.).
The electronics industry CEOs said that Europe can capture up to 60% of new electronics markets, and double the economic value of semiconductor component production in Europe within the next 10 years. “Advanced materials provide a path for breakthroughs and strong differentiation in silicon applications (Si-based, SOI, strain Si),” the report stated.
(It is worth noting that SOI is already well-represented in the areas cited for existing European strengths, with companies like NXP and ST producing enormous numbers of SOI-based chips for these markets.)Posted February 20, 2014 - Share this Buzz
CEA-Leti and STMicroelectronics presented an order-of-magnitude-faster FD-SOI Ultra-Wide-Voltage Range (UWVR) DSP at ISSCC ’14. The device was produced by ST in 28nm UTBB FD-SOI. It allows body-bias-voltage scaling from 0V to +2V, decreases minimum circuit operating voltage and supports clock-frequency operation of 460MHz at 400mV.
“This demonstration DSP shows that FD-SOI is blazing the trail for better portable and battery-powered products, using more efficient semiconductor chips, all the way down to the 10nm node,” said Philippe Magarshack, Executive Vice President, Design Enablement Services, STMicroelectronics.
The Leti/ST paper, entitled, “A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding Fmax Tracking,” was presented during Session 27, “Energy-Efficient Digital Circuits”. A demonstration kit was shown to ISSCC attendees. ISSCC – the International Solid-State Circuits Conference – is the flagship conference of the Solid-State Circuits Society. It is widely considered the premier forum for presenting advances in solid-state circuits and systems-on-a-chip.Posted February 18, 2014 - Share this Buzz
A new SemiWiki piece by Eric Esteve heralds Fujitsu’s 14nm FD-SOI benchmark results for a high-performance networking chip (click here to read the post). In “If you still think that FDSOI is for low performance IC only…”, Esteve explains why power is critical in these high-end ASICs. He then leads readers through the benchmark results and design considerations recently posted by Fujitsu Europe’s Chief Engineer in the LinkedIn “FD-SOI design community” group (LinkedIn members can click here to join the group). As Esteve notes, “…the great improvement on maximum power consumption on FDSOI technology is clearly due to the forward body bias effect, and such an improvement is a great benefit for high performance chips.” A highly-recommended read.Posted February 18, 2014 - Share this Buzz
Peregrine’s UltraCMOS® Global 1, the first reconfigurable RFFE system, includes a multimode, multiband power amplifier, post-PA switch, antenna switch and antenna tuner on a single chip. (Image courtesy: Peregrine Semiconductor)
RF-SOI powerhouse Peregrine Semiconductor has announced the Global 1 (press release here), billed as “the industry’s first reconfigurable RF front-end system”. The company says it features the industry’s first LTE CMOS PA with the same raw performance as the leading gallium arsenide (GaAs) PAs and has a 33-percent efficiency increase over other CMOS Pas.
Peregrine notes that this platform leverages 25 years of RF expertise with proven performance demonstrated by more than 2 billion RF-SOI units shipped.Posted February 7, 2014 - Share this Buzz
(Images courtesy: Debiotech)
Debiotech has debuted the JewelPUMP2, a new product dedicated to the Diabetes Type 2 market, based on Debiotech’s innovative JewelPUMP platform (press release here). By using its JewelPUMP platform, which is already in the industrialization phase and in preparation for the CE marking, Debiotech will be able to introduce the JewelPUMP2 shortly after its JewelPUMP for Type 1 patients, while ensuring the same degree of miniaturization, safety and reliability.
Back in 2009, Debiotech wrote in ASN (click here to read the article) about their Nanopump™, a volumetric membrane pump, at the heart of their systems. Co-designed by Debiotech and ST, and manufactured by ST, the pump consists of a membrane micromachined in an SOI wafer, which is in turn sandwiched between two Pyrex™ plates with throughholes. A piezoelectric actuator moves the membrane to compress and decompress the fluid in the pumping chamber.Posted February 7, 2014 - Share this Buzz
The extreme reliability of SiTime’s MEMS devices, using SOI technology, has enabled the company to cover all its MEMS oscillators and clock generators with a lifetime warranty (press release here).
SiTime contributed an excellent article to ASN a few years ago (click here to read it), explaining how their radical SOI-based approach put the company at the top of the fast-growing silicon-based timing market.
Now, SOI plus excellent design, quality, manufacturability and reliability, has enabled the company to cover all its MEMS oscillators and clock generators with a lifetime warranty. The devices are setting new standards in quality and reliability, Piyush Sevalia, Executive VP, Marketing at SiTime told ASN. The company has ascertained historic evidence of extremely low return failure rates (0.5 DPPM) with their SOI-based product lines.Posted January 31, 2014 - Share this Buzz
Europe needs to build a high-volume FD-SOI fab. Malcolm Penn, CEO of Future Horizons, said this in the firm’s annual forecast meeting, reported David Manners of ElectronicsWeekly (Click here to read his article.)
Last year, European Commission Vice President Neelie Kroes said, “I want to double our chip production to around 20% of global production. [...] It’s a realistic goal if we channel our investments properly.” (Click here for more on that story.)
To meet that goal, “The cornerstone of the European Leaders Group (ELG) report to Neelie Kroes, due in a week or two, should be the construction of a high volume FD-SOI wafer fab,” said Penn, as reported by Manners.
Despite resistance from Europe’s biggest semi players, “Building a volume production FD-SOI fab would be one of the most blatantly obvious things the ELG could do,” said Penn in the Manners piece, “it should be a cornerstone of the ELG plan. It would be a fantastic thing for them to do.”Posted January 31, 2014 - Share this Buzz
CMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. In 2013, they had 32 prototypes from 15 customers over three runs. The latest run embedded 25 different projects. Delivery of that run to users will be in Q2 2014.
“We have a total of 140 institutions/companies already using the PDK. Four MPW runs are scheduled in 2014, one for each quarter,” said Dr. Torki. MPW price is 15000 Euro/mm2.
“At CMP we fully support UTSOI model cards available in the process design-kit (PDK) for the 28nm FDSOI process,” explains Dr. Torki. The simulation model itself is available for Eldo, Spectre and Hspice. Cadence, Mentor and Synopsys make this model available as a standard feature thanks to a Leti-ST licensing agreement.
Look for news about availability of Leti’s new UTSOI2 model (click here for more information on the model) for 14nm FD-SOI in Q2.Posted January 31, 2014 - Share this Buzz
In a new edition (2013) of Taur and Ning’s Fundamentals of Modern VLSI Devices, the authors have added a chapter on SOI devices. The first edition of the book was widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. Reviewers on Amazon called the first edition of this book (1998) “best textbook I used” and the “Bible for microelectronic device engineers”. Now available as an eBook as well as in hardcover and paperback from Cambridge University Press (click here for details), this new edition will also be a valuable reference volume for practicing engineers involved in research and development in the electronics industry. As Professor Mark Lundstrom of Purdue noted, “The best book of its kind is now even better.”
A professor at UC San Diego, Yuan Taur spent twenty years at IBM’s T. J. Watson Research Center. Tak H. Ning is an IBM Fellow at the T. J. Watson Research Center, where he has worked for over 35 years.Posted January 23, 2014 - Share this Buzz