Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
Cadence has announced that its digital and signoff tools are now enabled for the current version of the GLOBALFOUNDRIES® 22FDX™ platform reference flow (see press release here). GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of software-controlled body bias to manage power, performance and leakage needed to create next-generation chips for mainstream mobile, IoT and consumer apps. In addition, the ARM® Cortex®-A17 processor was used to validate the implementation flow with the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution.
Cadence collaborated with GF on the development of the PDK for the 22FDX platform. The Cadence digital implementation tools support the capability of forward and reverse body bias (FBB/RBB) to optimize the performance/power tradeoffs, implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules. The digital implementation tools also support double-patterning aware parasitic extraction (PEX) and design for manufacturing (DFM).
“The 22FDX reference flow can enable customers to achieve real-time tradeoff between static power, dynamic power and performance to create innovative products,” said Pankaj Mayor, GF Biz Dev VP.
Posted November 27, 2015 - Share this Buzz
Synopsys has announced a comprehensive RTL-to-GDSII solution for GlobalFoundries 22nm technology process. The implementation and signoff tools from the Synopsys Galaxy™ Design Platform have been enabled for the current version of GF’s’ 22FDX™ platform reference flow. GF has qualified these tools to use body bias to manage power, performance and leakage to achieve optimal energy efficiency and cost effectiveness. (See the press release here.)
The Galaxy Design Platform supports body biasing techniques throughout the design flow, key to achieving optimal power and performance when using the 22FDX technology. Both forward body bias and reverse body bias are supported, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.
The reference flow using the Galaxy Design Platform is now available for early customer engagement.Posted November 23, 2015 - Share this Buzz
ATopTech, a leader in next-generation physical design solutions, has announced that their Aprisa™ and Apogee™ Place & Route tools are now enabled for the current version of the GlobalFoundries 22FDX™ platform reference flow. GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of using body bias to manage power, performance and leakage needed to create the next-generation chips for mainstream mobile, IoT and networking applications. (Read the press release here.)
ATopTech tools provide designers with the capability to intelligently and dynamically tune the power and performance of the next-generation system-on-chip (SoC) designs.Posted November 23, 2015 - Share this Buzz
Renesas Electronics will be coming out with chips built on 65nm FD-SOI technology by spring of 2016, reports EETimes Japan (see article in Japanese here, or a version translated by Google here). Although the story dates from February 2015, it has barely been covered in the English-speaking press. (FD-SOI expert Ali Khakifirooz talked about it briefly in a SemiWiki piece last month entitled FDSOI As a Multi-Node Platform, which you can read here). The chips can operate down to 0.4V, and consume 1/10th of the power of previous generations.
If you’ve been reading ASN right along, you might already know about it, from our piece last year on the Semicon Europa (’14) Low Power Conference (read it here). At the time, Renesas talked about a demo they’d done of a 32 bit CPU on 65nm SOTB (aka Silicon on Thin Box, which is a planar FD-SOI technology) with back bias that operates eternally (!!) with ambient indoor light.
Renesas has roots with Hitachi, which was an early SOTB/FD-SOI innovator. In fact, here at ASN we had a Hitachi/Renesas piece in ASN on SOTB back in 2006 (read it here), highlighting work they’d presented at IEDM in 2004. Then in 2010, Dr. Sugii, who’s a very highly respected researcher, wrote in ASN advocating SOTB for older nodes (read that here). So this has been in the works for a while. Does this not put these companies in an incredibly strong position for IoT?Posted October 28, 2015 - Share this Buzz
Tags: FD-SOI, Leti, GlobalFoundries, GF, 22nm, IoT, design, foundry, manufacturing
Leti has joined the GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support GF’s 22FDX™ technology platform. (Read the press release here.) Earlier this year, Leti assigned a team of experts to GF’s’ Dresden Fab 1 to support ramp up of the platform. As an ecosystem partner, Leti will provide GF customers with circuit-design IP, including its back-bias feature for FD-SOI, which enables exceptional performance at very low voltages with low leakage.
“This strategic partnership with GlobalFoundries positions Leti to help a broad range of designers utilize FD-SOI technology’s significant strengths in ultra-low-power and high performance in their IoT and mobile devices with 22nm technology,” said Marie Semeria, Leti CEO. “In addition, it gives both sides’ customers increased access to our respective technologies. This kind of partnership is a key part of Leti’s global strategy.”
28nm FD-SOI is on the Freescale roadmap for two key platforms in the company’s flagship i.MX line of embedded application processors:
- the i.MX 8 series for advanced graphics and performance, which is based on the ARM v8-A,
- and the i.MX 7 power efficiency series, which is based on the ARM v7-A.
This was shown in a presentation by Freescale VP Ron Martino during the Shanghai FD-SOI Forum. Entitled Smart Technology Choices and Leadership i.MX Applications Processors (you can download it here), it shows how increasing integration of diverse components and longer lived nodes are driving this move. That’s coupled with the “explosive” growth in smart vehicles and smart devices in the face of rising die costs.Posted October 6, 2015 - Share this Buzz
Using SiTimes’ SOI-MEMS based oscillator can extend battery life by a full day in some apps, Piyush Sevalia, Executive Vice President, Marketing for SiTime explained in a recent Planet Analog piece (read the whole thing here).
The traditional timing device is a quartz (passive crystal) resonator, which doesn’t draw any power itself. But it doesn’t save any either. As Piyush describes:
In a portable audio application for example, a SiT8021 oscillator operating at 3.072 MHz draws only 60 μ A compared to a quartz oscillator at 2.5 mA. In this case, the power consumption is 98% lower. This can effectively extend battery life by a full day – a huge improvement.
SiTime is a Bosch spin-off that’s now part of Megachips Corporation. The SiTime CTO first described their SOI-MEMS fabrication technology for ASN back in 2009 (read that here). Since then, they’ve shipped more than 300 million devices and captured 80% market share. Click here for more about SiTime’s SOI-MEMS solutions in ASN.Posted October 6, 2015 - Share this Buzz
In what may be a first for the MEMS industry, CEA-Leti has manufactured micro-accelerometers on 300mm wafers, a development that could lead to significantly lower MEMS manufacturing costs. And yes, those 300mm wafers are SOI wafers. These are “thick” SOI wafers, with an insulating BOx (buried oxide) layer of 2µm, and top silicon of 220nm.
The most advanced of Leti’s platforms is its M&NEMS technology based on detection by piezo-resistive silicon nanowires, which reduce sensor size and improve performances of multi-axis sensors. Leti’s inertial-sensor manufacturing concept enables the design and fabrication of combo sensors, such as three-axis accelerometers, three-axis gyroscopes and three-axis magnetometers on the same chip. This is a key component for IoT apps.
Leti’s M&NEMS concept, developed with 200mm technology, is currently being transferred to an industrial partner. Demonstration of this technology on 300mm wafers has shown very promising results.
In addition to lowering costs, manufacturing MEMS with 300mm technology enables 3D integration using MEMS CMOS processes in more advanced nodes than on 200mm, and the use of 3D through-silicon-vias (TSV), which is already available in 300mm technology. (Read the full Leti press release here.)Posted October 2, 2015 - Share this Buzz
A very successful two-day forum on FD-SOI and RF-SOI in Shanghai (September 2015) featured presentations from CEOs, CTOs and VPs at GF, ST, Leti, ARM, Verisilicon, Synapse Design, SITRI, Skyworks, Freescale, TowerJazz, Soitec, Qorvo and many more. Most of the presentations are now available on the SOI Consortium Website, and the rest are expected shortly, so keep checking back.
To download the “Design for FD-SOI” presentations, see the list here.
To download the “RF-SOI Workshop – Interconnected World” presentations, see the list here. (Presentations from all of the major SOI wafer suppliers are also available on this page.)Posted October 2, 2015 - Share this Buzz
In an EETimes interview, GlobalFoundries CEO Sanjay Jha said RF-SOI and FD-SOI were “…the right technologies at the right time,” (read the full piece here). He offered the new iPhone 6s as a proofpoint for the value of RF-SOI. For the company’s 22nm FD-SOI, he said production tape-out will be “…in the second half of 2016”. He sees big opps for FD-SOI with the fabless community in China, noting its suitability for mass market smartphones, automotive, power-critical IoT and analog devices.Posted September 24, 2015 - Share this Buzz
Soitec, the world’s SOI wafer leader, announced that the Board of Directors has named André-Jacques Auberton-Hervé as Chairman Emeritus (he founded Soitec together with Jean-Michel Lamure in 1992).
CEO Paul Boudre has been appointed Chairman of Soitec’s Board of Directors.
(Read the press release here.)Posted September 24, 2015 - Share this Buzz
FD-SOI champion STMicroelectronics has unveiled the company’s first System-on-Chip (SoC) products on FD-SOI. Two multi-core ARM SoC offerings – both for set-top boxes – have been announced. ST credits the 28nm FD-SOI silicon technology with providing highly-efficient RF and analog integration as well as outstanding power efficiency so that set-top box makers can now design very small fan-less systems. The announcements include:
- The Cannes Wi-Fi (STiH390): the first set-top-box SoC on the market integrating 4×4 11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This delivers state-of-the-art Wi-Fi performance and robustness required for reliable video delivery inside the home. (Read the press release here.)
- The new HD HEVC Liege3 family of chipsets for entry Set-Top-Box markets, with flavors for satellite, cable-market and IPTV set-top-box devices. More than just an upgrade of previous-generation devices, the new chipset family combines the latest architectures used in ST’s Cannes products with optimized IPs to deliver future-proof SoCs with high integration. ST says this will enable large-scale migration of entry set-top boxes towards HEVC (High Efficiency Video Coding). All chipsets are pin-to-pin compatible to facilitate design re-use among the different broadcast technologies. Software compatibility with ST’s Cannes SoC family enables OEMs to benefit from the comprehensive ecosystem in order to easily design innovative client boxes on multiple middleware products. (Read the press release here.)
Both are currently sampling to lead customers.Posted September 10, 2015 - Share this Buzz
Global specialty foundry TowerJazz and TowerJazz Panasonic Semiconductor Co. (TPSCo), the leading analog foundry in Japan, have announced breakthrough RF-SOI technology for next-generation 4G LTE smartphones and IoT devices. Through a collaborative effort, TowerJazz and its majority owned subsidiary, TPSCo, have developed a new 300mm RF-SOI process that can reduce losses in an RF switch by as much as 30% relative to current technology, improving battery life and boosting data rates. The technology achieves a record Ron-Coff figure of merit of sub-90fs and is now being sampled to a lead customer. (Read the press release here.)Posted September 10, 2015 - Share this Buzz
In an interview with EETimes, GlobalFoundries CEO Sanjay Jha indicated that more than 50% of the Dresden fab output could be FD-SOI by 2018 (read it here). Jha also told EETimes that More-than-Moore technologies can be considered the mainstream. In the piece entitled, Can GloFo and Europe’s chip firms unite? author Peter Clarke makes an excellent point that between the four European chip leaders (NXP-Freescale, ST, Infineon and GF), “…there is the digital, RF, power, mixed-signal and microcontroller expertise to make almost any sort of wireless sensor node or any other circuit for the Internet of Things. What is clear is that there is no longer a single vector of excellence in integrated circuit manufacturing.” A recommended read.Posted July 21, 2015 - Share this Buzz