Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
RF-SOI substrate guru Jean-Pierre Raskin, whose team at UCL* has driven the technology behind the most advanced wafer substrates for RF applications, has been awarded one of the highest honors in electronics: the prestigious Blondel Medal. The technology he pioneered is now in virtually all the world’s smartphones, and used by just about every RF foundry on the planet.
Dr. Raskin’s team first demonstrated a radical new approach (dubbed “trap rich” at the time) for improving the RF performance of high-resistivity (HR) SOI substrates back in 2003. Teams from UCL and Soitec then worked together on the industrialization, making it commercially available in SOI substrates for RF applications.
ASN readers will recognize this work from a 2013 article Dr. Raskin co-authored, Soitec and UCL Boost the RF Performance of SOI Substrates.
The result was a new wafer substrate Soitec named eSI, for enhanced Signal Integrity, and it’s been wildly successful. In fact Soitec estimates that more than one billion RF devices are produced each quarter using their eSI wafers. It’s been used for 2G, 3G and now 4G and LTE. With the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), the latest iterations of the Raskin team’s technology are in Soitec’s most advanced eSI90 wafers.
The Blondel Medal is the highest honor awarded by the SEE (the French Society for Electricity, Electronics, IT and Communications Technologies). It recognizes a researcher under 45 years old who has authored works or recorded exceptional achievements that have contributed to the advancement of science in Information and Communication Technology.
*UCL is the Université catholique de Louvain in Belgium. Click here to read more about Dr. Raskin’s research group.Posted February 8, 2016 - Share this Buzz
Design & Reuse, in partnership with GlobalFoundries, ST, Soitec and Leti, is sponsoring a series of FD-SOI IP Workshops around the globe. (Click here for more information.) These working days aim at sharing information about IP that’s currently available or is being designed for FD-SOI technology.
The first conference will take place during DATE in Dresden on 14 March 2016. Following that, conferences will also be held in Bangalore in April, Shanghai in September, and Grenoble in December.
Short summary submissions are now being solicited from designers offering IPs that are either currently in validation, are already silicon-proven, or are in production. The deadline for submissions to the Dresden event is 15 February. A prize will be awarded to the most innovative IP.
FD-SOI specific design flow or module presentations are also welcome.
The organizers are all members of the European Things2Do program (read about that here), which includes about 50 partners working on the FD-SOI ecosystem.Posted February 3, 2016 - Share this Buzz
Mentor Graphics is collaborating with GlobalFoundries on 22nm FD-SOI to qualify the Mentor® RTL to GDS platform for the current version of GlobalFoundries 22FDX™ platform reference flow. (Read the press release here.) This includes including Mentor’s RealTime Designer™ physical RTL synthesis solution and Olympus-SoC™ place & route system. In addition, Mentor and GF are working on the development of the Process Design Kit (PDK) for the 22FDX platform. The PDK includes support for the Mentor Calibre® platform, covering design rule checking (DRC), layout vs. schematic (LVS) and metal fill solutions for 22FDX. These solutions help mutual customers optimize their designs using the capability of 22FDX technology to manage the power, performance and leakage.
“We are collaborating closely with Mentor Graphics on enabling their products to help customers realize the benefits of the 22FDX platform,” said Pankaj Mayor, vice president of Business Development for GlobalFoundries. “The qualification of Mentor tools for implementation flows and design verification will help designers to achieve an optimal balance between power, performance and cost.”
The next release of the 22FDX PDK will put GF’s differentiated DFM capabilities into the hands of designers, says a Mentor spokesperson, ensuring delivery of high-quality designs and ensuring faster ramps to production.Posted December 23, 2015 - Share this Buzz
RF-SOI pioneer Peregrine Semiconductor has introduced the UltraCMOS® PE44820, an 8-bit digital phase shifter designed for active antenna apps, covering a 358.6-degree phase range. (Read the press release here.)
The UltraCMOS® PE44820 is a monolithic, digitally controlled product made for easy design-in and delivering exceptional phase accuracy and high linearity. Supporting a frequency range of 1.7 to 2.2 GHz, the PE44820 is ideal for optimizing the transmission phase angle in the wireless infrastructure and radar markets. It provides reliable and repeatable RF performance to applications such as antenna beamforming, distributed antenna systems (DAS) and phased-array antennas, says the company.
The PE44820 is also capable of extended frequency operation from 1.1 to 3.0 GHz for narrow band applications.
Samples, evaluation kits and volume-production parts are available now.Posted December 22, 2015 - Share this Buzz
VLSI Research Chip Insider has named Soitec CEO Paul Boudre to its roster of 2015 All Stars of the Semiconductor Industry. (See the announcement here.)
Boudre was cited for “…successfully re-organizing Soitec back to its core business as a leading innovative engineered substrate supplier. His first year results are already astounding, with very high growth rates.” Getting FD-SOI and RF-SOI into the mainstream figured among the notable accomplishments that elevated him to these ranks.
Congratulations to Paul Boudre and the entire Soitec team for this important recognition by one of the industry’s leading analyst groups.Posted December 19, 2015 - Share this Buzz
The IEEE S3S (SOI/3D/SubVt) has issued its call for papers for the 2016 conference (click here for details). The theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”. This industry-wide event gathers together widely known experts, contributed papers and invited talks focused on SOI Technology, Low-Voltage Devices/Circuits/Architectures, and 3D Integration. In addition to over 100 contributed and invited papers, the conference will feature prestigious Keynotes and a Hot Topics session.
For the first time, the Conference will include two Tutorials free-of-charge with Conference registration: one on FD-SOI Circuit Design and another on Technologies for Monolithic 3D Integration. A full-day short course addresses Energy Efficient Computing and Communications including RF circuit technology.
The paper submission deadline is the 15th of April 2016. As always, there will be a Best Paper Award and a Best Student Paper Award. But for the first time, the Best Student Paper Award includes a $1,000 prize from one of the conference’s industry sponsors.
The papers presented here give industry an excellent window on what’s coming next. For example, work demonstrating a viable integration path for stacked nanowires that was first presented in a Leti paper at the 2015 S3S Conference was awarded the Paul Rappaport IEEE Prize two months later at IEDM 2015.
S3S is a great conference – don’t miss it.Posted December 17, 2015 - Share this Buzz
With the acquisition of Maxim’s 8-inch fab in San Antonio, Texas, TowerJazz plans to quickly qualify its core specialty technologies, including its advanced Radio-Frequency Silicon-on-Insulator (RF-SOI) offering, to serve the substantial growth in demand from its customers. (See press release here.)
The proposed purchase will expand TowerJazz’s current worldwide manufacturing capacity, cost-effectively increasing production by approximately 28,000 wafers per month. The availability of additional capacity is expected to be needed to serve TowerJazz’s current and forecasted robust customer demand. TowerJazz and Maxim expect to close the transaction in January 2016, subject to customary closing conditions.Posted December 8, 2015 - Share this Buzz
CEA-Leti announced it has developed two techniques to induce local strain in FD-SOI processes for next-generation FD-SOI circuits that will produce more speed or lower power consumption and improved performance. (For more details, read the press release here.) Targeting the 22/20nm node, the local-strain solutions are dual-strained technologies: compressive SiGe for PFETs and tensile Si for NFETs. In addition to clearing the path to improved performance in FD-SOI technology, they preserve its excellent electrostatic integrity and its in situ performance tunability, due to back biasing.
The two techniques Leti developed can induce local stress as high as 1.6 GPa in the MOSFETs channel. Strained channels enable an increase in the on-state current of CMOS transistors. As a result, chips can deliver more speed at the same power, or reduce consumed power for longer battery life at the same performance. The first technique relies on strain transfer from a relaxed SiGe layer on top of SOI film. The second technique is closer to strain memorization methods and relies on the ability of the BOX to creep under high-temperature annealing.
“These two new techniques broaden the capabilities of Leti’s FD-SOI platform for next-generation devices, and further position the technology to be a vital part of the Internet of Things and electronics products of the future,” said Maud Vinet, head of Leti’s Advanced CMOS Laboratory.Posted December 8, 2015 - Share this Buzz
Toshiba has announced TaRF8, the next generation in the company’s TarfSOI™ (aka Toshiba advanced RF SOI) process, which is optimized for RF switch apps. The first product to use the technology is Toshiba’s new SP12T, enabling the lowest-class of insertion loss in the industry. Lowering insertion loss is recognized as particularly important in decreasing RF transmission power loss, which in turn means longer battery life for mobile devices. Sample shipments of SP12T RF switch ICs fabricated with the new process will start in January 2016. (See the press release here.)
Designed for use in smartphones, the SP12T RF switch is suitable for 3GPP™ GSM, UMTS, W-CDMA, LTE™ and LTE-Advanced standards.
Toshiba develops high-performance RF switch ICs using its in-house fab’s SOI-CMOS technology, which is suitable for integrating analog and digital circuits. By handling all aspects of production flow, from RF process technology development to the design and manufacturing of RF switch chips, Toshiba says it can quickly improve SOI-CMOS process technology in response to feedback from the development results of its own RF switch IC products. This IDM approach allows Toshiba to rapidly establish new process technologies suited to actual products, and to enter the market with products fabricated with the latest process technology.Posted November 30, 2015 - Share this Buzz
A recent NewElectronics article entitled ST’s FD-SOI transistor is set to give analogue designers a new knob to tune parameters, explores the many reasons that FD-SOI makes designers happy – even the analog folks. Editor Graham Pitcher talked to analog designer Andreia Cathelin, a senior member of STMicroelectronics’ technical staff. Among plenty of other things, she noted that with FD-SOI, “…transistors can offer the same analogue gain as they did at 130nm, but with the advantages of a 28nm channel.”(Read the full article here.)
It also helps simplify tuning in that you can change one parameter (linearity, noise, power consumption) without the change affecting the other parameters, she notes. For digital, she especially likes that FD-SOI can be biased up to +2V, compared to about 0.3V for bulk.
She concludes, ” “Analogue designers are happier; the transistor is back to offering good intrinsic performance and there is a ‘knob’ outside of the signal path. But if designers want to get the most out of FD-SOI, they will need to think about what they can do with that ‘knob’.”
A recommended read.Posted November 30, 2015 - Share this Buzz
Cadence has announced that its digital and signoff tools are now enabled for the current version of the GLOBALFOUNDRIES® 22FDX™ platform reference flow (see press release here). GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of software-controlled body bias to manage power, performance and leakage needed to create next-generation chips for mainstream mobile, IoT and consumer apps. In addition, the ARM® Cortex®-A17 processor was used to validate the implementation flow with the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution.
Cadence collaborated with GF on the development of the PDK for the 22FDX platform. The Cadence digital implementation tools support the capability of forward and reverse body bias (FBB/RBB) to optimize the performance/power tradeoffs, implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules. The digital implementation tools also support double-patterning aware parasitic extraction (PEX) and design for manufacturing (DFM).
“The 22FDX reference flow can enable customers to achieve real-time tradeoff between static power, dynamic power and performance to create innovative products,” said Pankaj Mayor, GF Biz Dev VP.
Posted November 27, 2015 - Share this Buzz
Synopsys has announced a comprehensive RTL-to-GDSII solution for GlobalFoundries 22nm technology process. The implementation and signoff tools from the Synopsys Galaxy™ Design Platform have been enabled for the current version of GF’s’ 22FDX™ platform reference flow. GF has qualified these tools to use body bias to manage power, performance and leakage to achieve optimal energy efficiency and cost effectiveness. (See the press release here.)
The Galaxy Design Platform supports body biasing techniques throughout the design flow, key to achieving optimal power and performance when using the 22FDX technology. Both forward body bias and reverse body bias are supported, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.
The reference flow using the Galaxy Design Platform is now available for early customer engagement.Posted November 23, 2015 - Share this Buzz
ATopTech, a leader in next-generation physical design solutions, has announced that their Aprisa™ and Apogee™ Place & Route tools are now enabled for the current version of the GlobalFoundries 22FDX™ platform reference flow. GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of using body bias to manage power, performance and leakage needed to create the next-generation chips for mainstream mobile, IoT and networking applications. (Read the press release here.)
ATopTech tools provide designers with the capability to intelligently and dynamically tune the power and performance of the next-generation system-on-chip (SoC) designs.Posted November 23, 2015 - Share this Buzz
Renesas Electronics will be coming out with chips built on 65nm FD-SOI technology by spring of 2016, reports EETimes Japan (see article in Japanese here, or a version translated by Google here). Although the story dates from February 2015, it has barely been covered in the English-speaking press. (FD-SOI expert Ali Khakifirooz talked about it briefly in a SemiWiki piece last month entitled FDSOI As a Multi-Node Platform, which you can read here). The chips can operate down to 0.4V, and consume 1/10th of the power of previous generations.
If you’ve been reading ASN right along, you might already know about it, from our piece last year on the Semicon Europa (’14) Low Power Conference (read it here). At the time, Renesas talked about a demo they’d done of a 32 bit CPU on 65nm SOTB (aka Silicon on Thin Box, which is a planar FD-SOI technology) with back bias that operates eternally (!!) with ambient indoor light.
Renesas has roots with Hitachi, which was an early SOTB/FD-SOI innovator. In fact, here at ASN we had a Hitachi/Renesas piece in ASN on SOTB back in 2006 (read it here), highlighting work they’d presented at IEDM in 2004. Then in 2010, Dr. Sugii, who’s a very highly respected researcher, wrote in ASN advocating SOTB for older nodes (read that here). So this has been in the works for a while. Does this not put these companies in an incredibly strong position for IoT?Posted October 28, 2015 - Share this Buzz