Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.


Revelations by semiwiki’s Eric Esteve that TSMC has filed a significant FD-SOI patent has generated a rush of speculation in the press and online forums.  In his piece When TSMC advocates FD-SOI…,  Esteve noted that TSMC’s patent for “Planar compatible FDSOI Design Architecture” (granted 14 May 2013) heralded the advantages as follows: “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.”

In a subsequent article in Electronics Weekly entitled TSMC Developing FD-SOI, David Manners concluded, “Clearly all mobile IC houses are looking at FD-SOI as an option because of its lower power potential. The fact that TSMC is developing the technology suggests that a customer or customers have enquired about using FD-SOI…”.

Posted September 17, 2014   -   Share this Buzz

PSemiWifiSwitch_RFSOIRF-SOI Pioneer Peregrine has announced new switches for wireless infrastructure and carrier-grade WiFi.  The UltraCMOS® PE42442 and PE42452 high-isolation, multi-throw switches address emerging requirements in wireless infrastructure equipment (read press release here).  The UltraCMOS® PE42424 RF Switch enables 802.11ac Wi-Fi access points to deliver faster data rates in high-density, bring-your-own-device environments, with 60 percent power handling increase and 75 percent smaller footprint (read press release here)

 

Posted September 17, 2014   -   Share this Buzz

In his recent piece, A couple of misconceptions about FD-SOI (3 September 2014), semiwiki blogger and IP expert Eric Esteve corrects some assertions surfacing about FD-SOI.  He reminds designers that to really benefit from FD-SOI, you want to leverage body-biasing. He explains how ST has automated the IP conversion process so it takes about half the time you’d normally expect. He also advocates FD-SOI for wearables and smartphones, as it provides both performance advantages and power savings.

Posted September 11, 2014   -   Share this Buzz

A thoroughly engaging and amusing LinkedIn Pulse piece by Bruce Kleinman comes down firmly on the side of 28nm FD-SOI.  Entitled 28nm: Home Improvements (posted 13 August 2014), it’s subtitled, “Welcome to 28nm! Make yourself comfortable, we’re going to be here for awhile.” He says (among lots of other things, including astute observations about 3D), “…in my book 28nm FD-SOI offers very similar performance/power characteristics to 20nm bulk silicon.” Kleinman’s currently SVP at HMicro, which is doing SOC solutions for demanding wireless apps and IoT.  He’s clearly got the street creds, arriving there by way of upper management at GlobalFoundries, Xilinx, HP, etc., having started out with a Stanford MSEE.  A good read – recommended.

Posted September 11, 2014   -   Share this Buzz

An excellent article in SST details Leti’s monolithic 3D (M3D) technology, as presented at the SemiconWest 2014 Leti Day (read the full article here). Written by Brian Cronquest, MonolithIC 3D’s VP Technology & IP, the piece covers a presentation given by Olivier Faynot, Leti’s Device Department Director, about “monolithic 3D technology as the ‘solution for scaling’.” Cronquest puts the big picture in perspective, while providing plenty of technical information. He ends by reminding readers that this and other key work will be further detailed at the IEEE S3S Conference (S3S = SOI + 3D + Subthreshold Microelectronics) October 6-9, 2014 at the Westin San Francisco Airport (see the conference website here).

Posted September 1, 2014   -   Share this Buzz

Murata and Peregrine Semiconductor have entered into a definitive agreement under which Murata will acquire all outstanding shares of Peregrine not owned by Murata (read full press release here). Peregrine will become a wholly owned subsidiary of Murata and continue with its current business model of solving the world’s toughest RF challenges. Peregrine supplies many wireless markets, including: smartphones, test & measurement, automotive, public safety radio and wireless infrastructure. Peregrine will also provide Murata with a strong portfolio of Intellectual Property Rights (IPR) covering the entire RF-SOI front-end.

“Murata is the world’s leading RF module and filter provider, and we have benefited from our many years of partnership with them. The combination of Murata’s leading products with Peregrine’s leading-edge SOI products will position us to compete aggressively in our chosen markets,” said Jim Cable, PhD, Chairman and CEO of Peregrine Semiconductor. “As part of the Murata team, we will be able to expand our existing partnership and speed the industry’s transition to an integrated, all-CMOS RF front-end. We remain committed to providing leading solutions to customers in all our current markets. We have huge respect for Murata’s capabilities, and look forward to jointly accomplishing great things.”

Posted September 1, 2014   -   Share this Buzz

imec’s 28Gb/s silicon photonics platform for optical interconnects and other optical applications will be included in an upcoming multiproject wafer run, reports R. Colin Johnson in EETimes (read the article here). These runs, which are on SOI wafers, are a joint effort by ePIXfab (founded by imec and Leti), Europractice IC and MOSIS.  They provide a cost-effective vehicle for fabless researchers in data and telecom.

Posted August 21, 2014   -   Share this Buzz

Peter Clark at Electronics360 wrote about a recent presentation by an STMicroelectronics research team using hafnium oxide for non-volatile embedded memory. (Read the full article here.) The results were given at a Leti memory workshop in June 2014. The team presented, “… results for a 16-kbit OxRAM test chip implemented in 28nm high-k metal gate process.” The project is under the aegis of a French government funded program for “…the development of magnetic RAM and resistive RAM embedded memory options for the 28nm fully-depleted silicon-on-insulator (FDSOI) manufacturing process and subsequent generations.” MCU tape-out is scheduled for the end of 2014.

Posted August 21, 2014   -   Share this Buzz

In RF-SOI news, Peregrine and RFMD announced that they have settled all outstanding claims between the companies (read press release here). The two companies have entered into patent cross licenses and have agreed to dismiss all related litigation.

“We are pleased that we have reached agreement with RF Micro Devices and resolved all of our outstanding litigation under terms that recognize Peregrine’s unique role in the invention and commercialization of RF SOI technology,” said Jim Cable, CEO of Peregrine Semiconductor.  “This agreement provides validation for the many ways in which Peregrine continues to expand the industry’s technological frontiers through both our inventions and commercial products. We look forward to continuing to solve our customers’ and partners’ toughest RF challenges.”

Bob Bruggeworth, president and CEO of RFMD, said, “We are very pleased to reach an agreement with Peregrine that recognizes the value of their patents and their contribution to the development of RF SOI. The signing of this patent cross‐license agreement allows RFMD to focus 100% on building the industry’s  leading portfolio of RF solutions, making this agreement very positive for both our company and our customers.”

Posted August 8, 2014   -   Share this Buzz

Gold Standard Simulations Ltd. (GSS) announced a multimillion dollar contract to license its complete TCAD/EDA tool suite to GlobalFoundries (see press release here).  The fully integrated and automated tool chain includes GARAND, the GSS ‘atomistic’ TCAD simulator; Mystic, the GSS statistical compact model extractor; and RandomSpice, the GSS statistical circuit simulator. The GSS tool suite is the world’s only fully integrated tool chain that performs simulation-based Design/Technology Co-Optimisation (DTCO) in advanced bulk, FD-SOI and FinFET technologies, including statistical variability and reliability.

Posted August 8, 2014   -   Share this Buzz

A new book entitled Silicon-On-Insulator (SOI) Technology, Manufacture and Applications (1st Edition) features contributions by experts at Soitec, GF, TSMC, Leti and more.

Billed as “a complete review of this rapidly growing high-speed, low-power semiconductor technology,” the book covers the entire SOI spectrum, from Moore to More than Moore.  It goes into SOI wafer technology,  electrical properties, modeling, PD-SOI, FD-SOI, FinFETs and junctionless transistors, RF, ultralow-power, photonics, memory, power and MEMS.  (See Table of Contents here.) This book should be a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics, as well as for electrical engineers in the automotive and consumer electronics sectors.

Silicon-On-Insulator (SOI) Technology, Manufacture and Applications is published by Woodhead Publishing, and is also available in print and ebook forms from major online retailers such as Amazon, Elsevier and Barnes & Noble. It was compiled and edited by Oleg Kononchuk, chief scientist at Soitec, France, and Bich-Yen Nguyen, a senior fellow at Soitec, USA.

Posted August 8, 2014   -   Share this Buzz

Soitec estimates that it has shipped enough of its eSI wafers to fabricate more than 1.4 billion RF front-end semiconductor devices. (Read the press release here.)  The proprietary Enhanced Signal Integrity™ (eSI) substrates are now the substrate of choice for manufacturing cost-effective and high-performance radio-frequency (RF) devices providing a power boost for 4G /LTE applications.

For eSI, Soitec and the Université catholique de Louvain (UCL) developed a technique that adds a “trap-rich” layer underneath the buried oxide, which freezes the parasitic surface conduction that’s inherent in any oxidized silicon substrate. (The technical details are clearly explained in an excellent ASN post by the Soitec and UCL team leaders – click here to read it.) Using a set of very specific patents, Soitec applied proprietary technology and accumulated knowledge to build the new eSI product line.

This substrate provides a raft of advantages to RF design. Because the trap-rich layer is built into the substrate, it reduces the number of process steps and relaxes design rules, leading to a highly competitive performance and die cost, including a smaller area per function. RF designers can therefore integrate diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss, better thermal conductivity and better signal integrity than other technologies. (Click here to read Soitec’s ASN post from December 2013 describing all the RF design challenges eSI answers.)

eSI_SoitecUCLwafer

Posted July 18, 2014   -   Share this Buzz

ST has posted a series of helpful website page for those new to FD-SOI – click here to see it. It starts with the basics, moves onto a discussion of how FD-SOI continues Moore’s Law,  and finishes with info on power efficiency, memories, analog and high-speed designs.

Posted July 15, 2014   -   Share this Buzz

An excellent article highlighting Leti’s work on monolithic 3D was recently published in the IEEE’s Spectrum magazine – click here to read it. In the article, Maud Vinet, manager of advanced CMOS at Leti says they’ve worked closely with ST to ensure manufacturability. “There is no major roadblock to the transfer of this technology to foundries,” she says in the article. “I feel very confident when I say that.”  In case you missed it, leaders of Leti’s 3D team also published a very informative piece right here in ASN – click here to read it.

Posted July 15, 2014   -   Share this Buzz

Specialty foundry TowerJazz announced the availability of an enhanced RF-SOI CMOS process design kit (PDK) for its 0.18µm process technology (see press release here). The kit was developed for use with Agilent Technologies’ Advanced Design System (ADS) software and targets a wide range of analog markets including front-end modules for mobile phones, tablets and WiFi terminals.

Posted June 17, 2014   -   Share this Buzz