Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
From RF-SOI pioneer Peregrine Semi comes a steady stream of new chips and design wins.
- Two UltraCMOS® MPAC–Doherty products—the PE46130 and PE46140 (press release here). These monolithic phase and amplitude controllers (MPAC) join the PE46120 in offering maximum phase-tuning flexibility for Doherty power amplifier (PA) optimization. Designed for the LTE and LTE-A wireless-infrastructure transceiver market, the MPAC–Doherty product family now extends from 1.8 to 3.8 GHz with three separate, pin-compatible parts.
- Design wins: Psemi’s high-linearity RF switches are designed into multiple DOCSIS 3.1 certified cable modems (press release here). CableLabs, the research and development consortium that develops the DOCSIS specification, has certified the first DOCSIS 3.1 cable modems. Of the certified modems, Peregrine Semiconductor’s RF switches—the UltraCMOS® PE42722 and PE42723—are designed into the cable modems that feature a band-select feature. The PE42722 and PE42723 are the only RF switches that enable dual upstream/downstream bands to reside in the same consumer premise equipment (CPE) device.
Psemi was honored with a 2015 Electronic Products “Product of the Year” award for its UltraCMOS® PE42020 True DC RF switch, the industry’s first and only RF integrated switch to operate from DC (0 Hz) to 8 GHz. (Press release here.)
- Psemi RF engineer Tero Ranta recently wrote a chapter summarizing the technical details behind how you use SOI CMOS for impedance tuning for the book “Tunable RF Components and Circuits—Applications in Mobile Handsets.” In an interview for Psemi’s SOI University, he said, “…the main point is that you can improve the performance of mobile devices by using tuning. And you can do it by using SOI technology, which is what we use at Peregrine.” He adds, “… there are many other places in the 4G and 5G smartphone RF front-ends that will require tuning going forward to optimize system performance.”
Posted April 29, 2016 - Share this Buzz
Registration is open for GlobalFoundries’ technical webinar, “How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology” (click here to go to the registration page). The webinar will cover the optimal steps to successfully implement ARM® Cortex®-A Series* processors using 22FDXTM 22nm FD-SOI technology.
GF Design Enablement Fellow Dr. Joerg Winkler will address:
- Differentiated features of 22FDX including body-bias
- Digital implementation flow using the Cadence tool suite
- Initial 22FDX power-performance-area (PPA) results of an ARM Cortex sub-module
- Understanding implementation details and results
This webinar will take place April 26, 2016 at10:00 am Pacific Time.
BTW, GF’s already done quite a few 22FDX-related webinars and videos – click here to see the current list.
~ ~ ~
* Per ARM, “Cortex-A processors are specifically designed to execute complex functions and applications such as those required by consumer devices like smartphones and tablets. Their performance efficiency is also making them an increasingly popular choice for servers and enterprise applications where large core clusters can be combined for optimal solutions.”Posted April 25, 2016 - Share this Buzz
GlobalFoundries recently announced availability of a new set of RF-SOI PDKs for the company’s 7SW SOI technology. GF, which has now delivered more than 20 billion RF-SOI chips for the world’s smartphones, tablets and more, notes that its 7SW SOI technology is optimized for multi-band RF switching in next-generation smartphones. It is also poised to drive innovation in IoT applications.
The new PDKs feature an interoperable co-design flow to help chip designers improve design efficiency and deliver differentiated RF-SOI front-end solutions in increasingly sophisticated mobile devices. (See press release here.) The new PDKs are designed to use with Keysight Technologies’ (formerly Agilent) Advanced Design System (ADS) EDA software, so designers can edit their designs in ADS using a single Si2 OpenAccess database without any interference.
“Our 7SW platform, with superior LNA, switch devices, and trap-rich substrates, offer improved devices reception, interference rejection, and battery life for fewer dropped calls and longer talk time,” said Peter Rabbeni, senior director of RF product marketing and business development at GlobalFoundries. “Our RF-SOI technology has gained significant industry traction for cellular front-end module applications, and the new RFIC interoperability feature will allow us to provide our 7SW customers additional design flexibility with a single PDK.”Posted April 7, 2016 - Share this Buzz
Three of the world’s More-than-Moore and SOI technology development powerhouses have signed a comprehensive agreement for ongoing collaboration and cooperation in developing new technologies for the emerging IoT market. SITRI of Shanghai, and CEA-Leti and Minatec of Grenoble will work together to accelerate the adoption of their latest technologies and create a global innovation ecosystem for emerging IoT applications (read the press release here).
The framework agreement broadly covers all joint areas of research at SITRI and Leti, including MEMS and sensors, 5G RF front ends, ultra-low power computing and communication, RF-SOI and FD-SOI.
In fact, the trio cites SOI as a key technology in the development of both Moore’s Law and “More than Moore” solutions for the IC industry, as it brings cost, performance, power and integration advantages to the areas of ICs, RF, MEMS, and communications.
“We are confident that this collaboration will be positive for China’s electronics industry, as well as for the Grenoble region’s growing SOI technology ecosystem,” said MINATEC Director Jean-Charles Guibert.
Adds Marie-Noëlle Semeria, CEO of Leti, “Through this partnership, SITRI, MINATEC, CEA-Leti and the entire ecosystem will be able to promote and extend this ecosystem to SOI partners worldwide, and provide SOI solutions to the emerging Chinese IoT market.”
“MINATEC is a world-class international innovation center that fosters a wide range of leading-edge IoT technology research and development which is home to CEA-Leti, the renowned international research institute in microelectronics,” said Charles Yang, President of SITRI. “Through this agreement and SITRI’s established platform for ‘More than Moore’ commercialization, we can accelerate the adoption of these latest technologies and create a global innovation ecosystem for emerging IoT applications.”Posted April 5, 2016 - Share this Buzz
Coupling Wave Solutions (CWS) has a new productivity tool called SiPEX, which enables RF-SOI designers to increase the number of design iterations—including Spice simulation—up to 10 times in the same time frame.
“With SiPEX, RF switch designers will be able to make their design changes in less than 15 minutes and obtain a few decibels (dB) of variation over silicon measurements in simulation. This is a dramatic improvement over current productivity levels,” said Brieuc Turluche, CEO of CWS.
“State-of-the-art RF front-end components require advanced design methodologies and tools. SiPEX helped us improve our productivity and close the gap between simulation and silicon measurements when optimizing the linearity of our chips,” said Greg Caltabiano, CEO of ACCO, a fabless semiconductor company developing innovative highly integrated semiconductor solutions for IoT and smart phone RF Front Ends.
With SiPEX, RF designers can either evaluate more design implementations in any given time frame, or accelerate the tape out to the RF-SOI foundry, shortening the time-to-market. SiPEX provides field solver-like accuracy. In addition, an RF-SOI foundry can back-annotate the silicon measurements in their PDK and ensure that Spice simulation with SiPEX will match the actual silicon measurements.
SiPEX is available as a plug-in for generic interconnect parasitic extraction tools including Mentor Graphic’s Calibre®.Posted March 31, 2016 - Share this Buzz
Don’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.
As of this writing, the following keynote speakers have been confirmed:
- Ron Martino, NXP : “Advanced Innovation and Requirements for Future Smart, Secure and Connected Applications”
- Peter Gammel, Skyworks : “RF front end requirements and roadmaps for the IoT”
- Nick Yu, Qualcomm : topic TBA
Invited speakers include:
- Jamie Schaffer, GlobalFoundries : topic TBA
- Philippe Flatresse, ST Microelectronics : “Body bias and FDSOI for Automotive”
- Akram Salman, Texas Instruments : “ESD for advanced digital and analog technologies”
- Xavier Garros, CEA-Leti : “Reliability of FDSOI”
As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.
Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :
For current information on the conference visit the S3S website at: http://s3sconference.org/
LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.Posted March 23, 2016 - Share this Buzz
EDI CON China 2016, taking place April 19-21 in Beijing at the China National Convention Center (CNCC) will feature a keynote talk by GlobalFoundries‘ Peter Rabbeni, Sr. Director, RF BU Business Development & Product Marketing. The talk, entitled, “RF SOI: Revolutionizing Radio Design Today and Driving Innovation for Tomorrow”, will kick off the newly added RF-SOI Technology Track. The SOI Track will also feature talks and workshops from Peregrine Semiconductor, TowerJazz, Simgui, AnalogSmith and Shanghai Jiao Tong University. The talks will cover substrate engineering, design enablement, CMOS power amplifier design techniques and highly integrated control devices.
Mr. Rabbeni’s keynote talk will cover how there has been dramatic growth in RF SOI over the last several years in its continued march in driving performance improvement, cost reduction and architecture innovation between the transceiver and the antenna in mobile radios. No other radio technology in recent memory has had the impact that RF SOI has had in this respect. With standards becoming increasingly more challenging and the pending introduction of 5G, RF SOI is expected to continue to play an important role in the development of innovative architectures. His presentation will explore where we have been, why and where we may be headed with this technology. Substrate engineering and SOI device technology is reviewed in detail in Microwave Journal’s October 2015 cover story at http://www.microwavejournal.com/articles/25255.
More information is available at www.ediconchina.com.Posted March 18, 2016 - Share this Buzz
RF-SOI pioneer Peregrine Semiconductor has announced the UltraCMOS® PE4314, a 75-ohm glitch-less RF digital step attenuator (DSA). This new DSA extends Peregrine’s existing glitch-less DSA portfolio to 75 ohms. The PE4314 is ideal for wired broadband applications in cable/satellite customer premises equipment (CPE) and infrastructure equipment.
“As the founders of RF-SOI, Peregrine is recognized as a performance leader in RF products,” says Kinana Hussain, director of marketing at Peregrine Semiconductor. “Our products offer best-in-class performance and proven quality and reliability. The PE4314 is a testament to staying true to this philosophy. Peregrine introduced the world’s first single-chip DSA in 2004, and we are now expanding our DSA portfolio to include this 75-ohm solution to solve one of our customers’ biggest challenges—attenuation state transition glitches.”Posted February 12, 2016 - Share this Buzz
RF-SOI substrate guru Jean-Pierre Raskin, whose team at UCL* has driven the technology behind the most advanced wafer substrates for RF applications, has been awarded one of the highest honors in electronics: the prestigious Blondel Medal. The technology he pioneered is now in virtually all the world’s smartphones, and used by just about every RF foundry on the planet.
Dr. Raskin’s team first demonstrated a radical new approach (dubbed “trap rich” at the time) for improving the RF performance of high-resistivity (HR) SOI substrates back in 2003. Teams from UCL and Soitec then worked together on the industrialization, making it commercially available in SOI substrates for RF applications.
ASN readers will recognize this work from a 2013 article Dr. Raskin co-authored, Soitec and UCL Boost the RF Performance of SOI Substrates.
The result was a new wafer substrate Soitec named eSI, for enhanced Signal Integrity, and it’s been wildly successful. In fact Soitec estimates that more than one billion RF devices are produced each quarter using their eSI wafers. It’s been used for 2G, 3G and now 4G and LTE. With the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), the latest iterations of the Raskin team’s technology are in Soitec’s most advanced eSI90 wafers.
The Blondel Medal is the highest honor awarded by the SEE (the French Society for Electricity, Electronics, IT and Communications Technologies). It recognizes a researcher under 45 years old who has authored works or recorded exceptional achievements that have contributed to the advancement of science in Information and Communication Technology.
*UCL is the Université catholique de Louvain in Belgium. Click here to read more about Dr. Raskin’s research group.Posted February 8, 2016 - Share this Buzz
Design & Reuse, in partnership with GlobalFoundries, ST, Soitec and Leti, is sponsoring a series of FD-SOI IP Workshops around the globe. (Click here for more information.) These working days aim at sharing information about IP that’s currently available or is being designed for FD-SOI technology.
The first conference will take place during DATE in Dresden on 14 March 2016. Following that, conferences will also be held in Bangalore in April, Shanghai in September, and Grenoble in December.
Short summary submissions are now being solicited from designers offering IPs that are either currently in validation, are already silicon-proven, or are in production. The deadline for submissions to the Dresden event is 15 February. A prize will be awarded to the most innovative IP.
FD-SOI specific design flow or module presentations are also welcome.
The organizers are all members of the European Things2Do program (read about that here), which includes about 50 partners working on the FD-SOI ecosystem.Posted February 3, 2016 - Share this Buzz
Mentor Graphics is collaborating with GlobalFoundries on 22nm FD-SOI to qualify the Mentor® RTL to GDS platform for the current version of GlobalFoundries 22FDX™ platform reference flow. (Read the press release here.) This includes including Mentor’s RealTime Designer™ physical RTL synthesis solution and Olympus-SoC™ place & route system. In addition, Mentor and GF are working on the development of the Process Design Kit (PDK) for the 22FDX platform. The PDK includes support for the Mentor Calibre® platform, covering design rule checking (DRC), layout vs. schematic (LVS) and metal fill solutions for 22FDX. These solutions help mutual customers optimize their designs using the capability of 22FDX technology to manage the power, performance and leakage.
“We are collaborating closely with Mentor Graphics on enabling their products to help customers realize the benefits of the 22FDX platform,” said Pankaj Mayor, vice president of Business Development for GlobalFoundries. “The qualification of Mentor tools for implementation flows and design verification will help designers to achieve an optimal balance between power, performance and cost.”
The next release of the 22FDX PDK will put GF’s differentiated DFM capabilities into the hands of designers, says a Mentor spokesperson, ensuring delivery of high-quality designs and ensuring faster ramps to production.Posted December 23, 2015 - Share this Buzz
RF-SOI pioneer Peregrine Semiconductor has introduced the UltraCMOS® PE44820, an 8-bit digital phase shifter designed for active antenna apps, covering a 358.6-degree phase range. (Read the press release here.)
The UltraCMOS® PE44820 is a monolithic, digitally controlled product made for easy design-in and delivering exceptional phase accuracy and high linearity. Supporting a frequency range of 1.7 to 2.2 GHz, the PE44820 is ideal for optimizing the transmission phase angle in the wireless infrastructure and radar markets. It provides reliable and repeatable RF performance to applications such as antenna beamforming, distributed antenna systems (DAS) and phased-array antennas, says the company.
The PE44820 is also capable of extended frequency operation from 1.1 to 3.0 GHz for narrow band applications.
Samples, evaluation kits and volume-production parts are available now.Posted December 22, 2015 - Share this Buzz
VLSI Research Chip Insider has named Soitec CEO Paul Boudre to its roster of 2015 All Stars of the Semiconductor Industry. (See the announcement here.)
Boudre was cited for “…successfully re-organizing Soitec back to its core business as a leading innovative engineered substrate supplier. His first year results are already astounding, with very high growth rates.” Getting FD-SOI and RF-SOI into the mainstream figured among the notable accomplishments that elevated him to these ranks.
Congratulations to Paul Boudre and the entire Soitec team for this important recognition by one of the industry’s leading analyst groups.Posted December 19, 2015 - Share this Buzz
The IEEE S3S (SOI/3D/SubVt) has issued its call for papers for the 2016 conference (click here for details). The theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”. This industry-wide event gathers together widely known experts, contributed papers and invited talks focused on SOI Technology, Low-Voltage Devices/Circuits/Architectures, and 3D Integration. In addition to over 100 contributed and invited papers, the conference will feature prestigious Keynotes and a Hot Topics session.
For the first time, the Conference will include two Tutorials free-of-charge with Conference registration: one on FD-SOI Circuit Design and another on Technologies for Monolithic 3D Integration. A full-day short course addresses Energy Efficient Computing and Communications including RF circuit technology.
The paper submission deadline is the 15th of April 2016. As always, there will be a Best Paper Award and a Best Student Paper Award. But for the first time, the Best Student Paper Award includes a $1,000 prize from one of the conference’s industry sponsors.
The papers presented here give industry an excellent window on what’s coming next. For example, work demonstrating a viable integration path for stacked nanowires that was first presented in a Leti paper at the 2015 S3S Conference was awarded the Paul Rappaport IEEE Prize two months later at IEDM 2015.
S3S is a great conference – don’t miss it.Posted December 17, 2015 - Share this Buzz
CEA-Leti has signed an agreement with Keysight Technologies (formerly the Agilent/HP test group), the industry-leading device-modeling software supplier, to adopt Leti’s UTSOI extraction flow methodology within Keysight’s device modeling solutions for high-volume SPICE model generation. (Read the press release here.)
“This collaboration between Leti and Keysight will strengthen the global FD-SOI ecosystem by providing an automatic extraction flow for building model cards associated with the Leti-UTSOI models, which are already available in all the major SPICE simulators,” said Marie Semeria, Leti’s CEO. “This professional, automatic extraction-flow solution will address designers’ needs as they weigh FD-SOI’s benefits over competing solutions for the 28nm technology node and below.”
Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. Power optimization is of course a key component in SOC design. Automatic extraction helps ensure that the power intent specified by the designer in the simulated transistors will really match what will ultimately be seen in silicon.
The simulation of the Leti-UTSOI compact model, which is the first complete compact model dedicated to Ultra-Thin Body and Box and Independent Double Gate MOSFETs (aka FD-SOI), is currently available in Keysight’s modeling and simulation tools. This agreement expands the collaboration to include the extraction flow and will enable device-modeling engineers to efficiently create Leti-UTSOI model cards for use in Process Design Kits (PDKs).Posted December 14, 2015 - Share this Buzz