Industry Buzz

Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world?  Check
out our Industry Buzz – now featuring regular updates.


After a very successful first edition in 2013, the 2014 IEEE S3S will take place in San Francisco, 6-9 October, 2014 (click here for details). IEEE S3S combines the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, and adds a parallel track in 3D Integration. The technical sessions will be preceded by two one-day Tutorial Short Courses. Fundamental Classes are also offered. The Call for Papers submission deadline has been set for 5 May 2014 (click here for more info).

Posted April 9, 2014   -   Share this Buzz

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The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates matching those of more conventional CVD techniques. The system will be used by both internal and external researchers in fabricating a broad range of semiconductor-based devices including leading-edge CMOS transistors, MEMS, ICs built with the latest in through-silicon-via (TSV) technology, advanced LEDs and solar cells. Altatech is a subsidiary of Soitec (the world leader in SOI wafer manufacturing). AltaCVD systems have been used extensively in R&D and pilot production facilities throughout Europe; however, the University of Washington’s order represents the first such system to be delivered to a North American university R&D and pilot production facility.

Dr. Michael Khbeis, acting director of the WNF, said, “The AltaCVD system provides a unique capability that enables researchers to deposit conformal metal films for TSV applications as well as metal oxides and nitrides for high-k dielectrics and piezoelectric materials. The higher deposition rate enabled by pulsed CVD makes ALD films a tractable solution for scale-up paths toward high-volume manufacturing for our researchers and industrial clients. This ensures a viable pathway from academia to real economic impact in our region.”

Posted April 9, 2014   -   Share this Buzz

Tronics_SOI_MEMS      Leti_NMEMS_Ultimes_V2

A year after announcing the industrialization of CEA-Leti’s breakthrough M&NEMS technologies, Tronics has successfully designed and manufactured the first batch of six-degrees-of-freedom (6DOF) MEMS chips, with 3 accelerometers and 3 gyroscopes on a single die (press release here). Built on SOI wafers, with a die size of less than 4mm2, this 6DOF MEMS chip is one of the smallest in the industry, and Tronics says further optimization will make it the smallest. Besides its size advantage, the piezoresistive nanowire based technology significantly decreases power consumption and allows manufacturing of all sensor types (accelerometers, gyroscopes, magnetometers, pressure sensor and microphone) using a common process flow.

This first functional batch is an important milestone towards high volume production. The industrialization work will continue through 2014, with the first commercial samples available in Q4 2014. An ASIC is also being designed and will be available in 2014 to complete the sensor platform. In addition to the 6DOF device, Tronics has also designed a very compact 9DOF monolithic MEMS. Samples will be available by the end of this year.

Target applications for this new generation of inertial devices are those where size and/or power are key: wearable devices, smartphones and tablets.

Posted April 9, 2014   -   Share this Buzz

A new SemiWiki post by Dr. Eric Esteve of IPnest entitled, The Technology to Continue Moore’s Law… (click here to read it) argues that FD-SOI is the right choice.  He explores cost and manufacturing considerations, and looks at the design issues in logic, memories and analog.  A highly recommended read.

Posted March 26, 2014   -   Share this Buzz

SEH_SOI

(Courtesy: SEH, weSRCH)

 

A presentation by Shin‐Etsu Handotai (SEH, the world’s largest wafer supplier) detailing the company’s line-up of wafers for FD-SOI and SOI-FinFET is now available on weSRCH (click here to access it).

SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since 1988. In 1997, SEH introduced SOI wafers produced using Soitec’s Smart CutTM technology. (Soitec is the world leader in SOI wafer production.) In 2012, the two companies extended their licensing agreement and expanded their technology cooperation.

The SEH presentation on weSRCH was presented in Shanghai in October 2013. The company reiterated that it has achieved the quality, has the requisite experience, and has enough factories for rapid expansion.

Posted March 26, 2014   -   Share this Buzz

Puce micropompe Flumin3

(Courtesy: CEA-Leti)

 

Eveon and CEA-Leti have demonstrated liquid-pumping for smart drug delivery in the bolus mode using a silicon-based micro-pump fabricated with a standard MEMS process. (Read full press release here.)

The milestone is the first functional micro-pump integration using MEMS standard process on Leti’s 200mm line. It is a result of FluMin3, Eveon and Leti’s three-year joint-development project to produce an automatic drug-delivery system integrating a MEMS micro-pump that reduces patient discomfort by delivering medicine with very high accuracy, minimal loss and high flow rates.

The micro-pump is based on core technology initiated by Eveon and IMEP-LAHC. The pump demonstrator is made from SOI wafers, which include a thin deformable membrane sealed over a fluidic cavity and fluidic valves determining inlet and outlet. A dedicated electromagnetic actuator developed by Cedrat Technologies shapes the membrane.

Posted March 26, 2014   -   Share this Buzz

FDSOIwafer

 

(Image courtesy: SEMI, Soitec, weSRCH)

An excellent Soitec presentation from Semicon Japan entitled Innovative Substrates in the Mobile Era is now available on weSRCH (click here to view it). Given by Soitec COO Paul Boudre, it details the role of SOI wafers in RF and FD-SOI for mobile.

Posted March 19, 2014   -   Share this Buzz

SemiconEuropa14_Grenoble

For the first time, SEMICON Europa will be held in Grenoble, France. The greater Grenoble region is home to industry leaders leveraging and researching SOI and related advanced substrates, including Soitec, Leti and  ST.

SEMI has now announced the “Call for Papers” for technical sessions and presentations for SEMICON Europa 2014, which takes place October 7-9. Technical presentation abstracts are due April 30

SEMICON Europa (www.semiconeuropa.org) will highlight — in addition to the traditional semiconductor manufacturing segment — new areas like electronic components and design as well as electronic applications for energy efficiency, imaging, healthcare and security. Many of these technologies are emerging from the innovative companies in and around Grenoble.  Last summer, the French government said that the new Nano2017 would make Grenoble one of the three pillars (along with what could be considered the other European SOI capitals: Dresden/GlobalFoundries and Eindhoven/NXP) of the European Horizon2020 program, which launched in January 2014 (read about that here).

The Grenoble region, with established and emerging technology companies, has been characterized as “one of the Top 5 most innovative areas in the world” by Forbes Magazine.  From now on, Semicon Europa will be rotating between Dresden and Grenoble.

Posted March 19, 2014   -   Share this Buzz

 

ST_EETimesAsia_FDSOI

A powerful, detailed article in EETimes-Asia details how FD-SOI Supports Moore’s Law (click here to read it).  Written by Laurent Remont, ST’s VP and GM for Technology and Product Strategy, Embedded Processing Solutions, it explores FD-SOI’s advantages in terms of price, power and performance versus planar bulk CMOS and FinFETs and 28nm and 14nm.

Remont explains how structurally it is the most cost-effective sub-30nm process technology because FD-SOI is much simpler. In an interesting twist, he goes on to describe how forward body biasing (FBB) allows for dynamic power / leakage / frequency tuning linked to datacenter load. “With this, energy use would be proportional to workload and FD-SOI could reduce global data center power by up to 50 per cent,” he says.

In terms of performance, he says, “…the switch from 28nm Bulk CMOS to 28nm FD-SOI can improve circuit speed by as much as 35%. Even with this performance, FD-SOI transistors run cooler, because of lower leakage, wider voltage scaling and FBB all leading to higher power efficiency.

He concludes that FD-SOI will enable the industry to validate Moore’s Law down to 10nm. A highly recommended read.

Posted March 19, 2014   -   Share this Buzz

Soitec Sr. VP (and FD-SOI wafer guru) Christophe Maleville has written a very good, high-level piece in the Global Semiconductor Alliance (GSA) Forum.  Entitled Technology Selection Implications Intensify and Options are Limited, the piece examines cost-per-gate trends and explores roadmap options. He shows how FD-SOI provides a path forward with continued scalability, significant cost advantage and execution risk reduction vs. all other options. (Read the article here – GSA membership not required.)

 

 

Posted February 28, 2014   -   Share this Buzz

Semiwiki blogger Paul McLellan has written an excellent piece on the FD-SOI analog-to-digital converter (ADC) that ST presented recently at ISSCC. (Read the article here.)  He notes, “This is a very high performance ADC and thus an example of complex high-precision analog design in FD-SOI.”  He concludes, “Together with the low-power capability of the 28nm CMOS UTBB FDSOI technology, ST could reach 10GS/s operation while keeping the power consumption at 32mW under 1V supply with a block that is just 0.009mm2.” Recommended technical read.

 

Posted February 28, 2014   -   Share this Buzz

Altatech, a CVD/equipment subsidiary of SOI wafer leader Soitec, announced a new collaborative partnership to research and develop materials for the next generation of high-efficiency solar cells. Joining forces with Helmholtz-Zentrum Berlin für Materialien und Energie (HZB), a member of the Helmholtz Association of German Research Centres, Altatech will be working on new classes of materials and innovative device structures for photovoltaic and photocatalysis applications. Altatech will install a new single-substrate multi-chamber solution (an AltaCVD system) at HZB’s newly constructed Energy Materials In-situ Laboratory (EMIL) at the synchrotron light source BESSY II facility in Berlin. (Read press release here.)

Posted February 28, 2014   -   Share this Buzz

ST_ARMCon_FDSOI_slide39

(Courtesy: Synopsys, STMicroelectronics, ARM)

An excellent ARM TechCon 2013 video on FD-SOI for designers is now posted on the Synopsys site. David Jacquet from ST shares the company’s FD-SOI approach to delivering optimized energy efficient solutions for the SoC market. Jacquet currently leads ST’s architecture activities for energy efficient high performance CPU/GPU implementations. In his presentation (click here to view it) entitled, “Energy Efficient Implementation of ARM® Cortex©-A57/-A53 Processor Cores in FD-SOI Process Technology”, he begins with with an overview of the FD-SOI process technology as an enabler for high performance / low power design. Highlights from the low power implementation and verification methodology developed with Synopsys, including results and best practices, are also presented. This is a technical presentation, covering ST’s process technology and ARM-core based SoC product roadmap. ARM TechCon is ranked one of the top three must-attend events in the embedded industry. Highly recommended viewing.

Posted February 20, 2014   -   Share this Buzz

Citing SOI in the Power family of high-performance processors, Chipworks concludes that IBM is a major source of chip innovation. In a recent EETimes article (read it here), which charts IBM developments at the transistor level over the last decade, the article notes that “..the 32 nm technology used to fabricate the IBM Power7+ represents an extraordinary technical achievement. IBM continues to be one of the technology leaders in the global semiconductor industry.”  The article has excellent charts and pictures, and is a recommended read for anyone interested in the evolution of leading-edge SOI-based processors over the last decade.

Posted February 20, 2014   -   Share this Buzz

“High performing low power digital technology based on SOI” is an important part of the detailed plan submitted February 14th by the Electronics Leaders’ Group (ELG) to European Commission Vice-President Neelie Kroes.  (Press release here.) The group recommends the EU focus on:

  • Areas were Europe is strong – automotive, energy, industrial automation and security. The target is to double current production in the next 10 years.
  • New high growth areas, in particular Internet of Things (IoT) and the development of ‘Smart-X’ markets (e.g. smart homes, smart grids etc.).

The electronics industry CEOs said that Europe can capture up to 60% of new electronics markets, and double the economic value of semiconductor component production in Europe within the next 10 years.  “Advanced materials provide a path for breakthroughs and strong differentiation in silicon applications (Si-based, SOI, strain Si),” the report stated.

(It is worth noting that SOI is already well-represented in the areas cited for existing European strengths, with companies like NXP and ST producing enormous numbers of SOI-based chips for these markets.)

Posted February 20, 2014   -   Share this Buzz