Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
SureCore’s ultra-low power SRAM technology on 28nm FD-SOI saves 70% in read/write power and reduces leakage by 30% compared to 40nm bulk implementations, writes SemiconductorEngineering Editor-In-Chief Ed Sperling (read the article here). Hitting the sweet spot for mobile, IoT and wearables, SureCore recently raised $1.6 million in funding.Posted February 23, 2015 - Share this Buzz
SiTime’s SOI-MEMS solution is a key part of a new realtime health and fitness tracking solution from MegaChips called “frizz”. MegaChips has announced a partnership with Bosch Sensortec to provide a complete reference design for use of frizz in smartphones, wearables and other personal devices allowing consumers to monitor their activities in real time (read the press release here).
This marks SiTime’s first major announcement since becoming a subsidiary of Mega chips. SiTime leverages SOI-MEMS for high-performance, ultra-low power, ultra-slim timing solutions. (SiTime contributed an excellent piece to ASN a few years ago explaining their SOI edge – you can still read it here.)
Piyush Sevalia, SiTime marketing EVP, said, “SiTime’s groundbreaking MEMS and programmable analog technologies allow us to deliver game-changing MEMS timing solutions. Our MHz and kHz solutions provide the best accuracy, the smallest size and the lowest power, all of which are ideally suited for wearable electronics and internet of things (IoT).”
Frizz is a motion sensor hub with a 32bit DSP based motion engine that can realize high performance calculations used in processing algorithms with ultra-low power consumption in lieu of a microprocessor. MegaChips’ ultra-low power frizz, combined with the SiTime SiT1602 programmable MHz oscillator and Bosch Sensortec MEMS sensors provide more meaningful data, easy interpretation, higher accuracy and ultra-low power critical for longer battery life.
The joint frizz and Bosch Sensortec solution is available now from MegaChips (extensive information is available here).Posted February 23, 2015 - Share this Buzz
A recent post by Eric Esteve on SemiWiki, entitled Sony Endorses FD-SOI to Attack Wearable & IoT (click here to read it) delves into some of the technical and design details of Sony’s Tokyo presentation on a 1mW 28nm FD-SOI GPS. (The full presentation is available here. Or click here to read the ASN overview of all the Tokyo presentations.) For the design community, IP expert Esteve talks about how Sony dramatically lowered the supply voltage, and looks at active power consumption, leakage, intrinsic gain and noise. He concludes, “FD-SOI penetration in consumer applications has started.”Posted February 17, 2015 - Share this Buzz
ARM is working on FD-SOI libraries, and the ecosystem is now there, says David Manners of Electronics Weekly. In two separate pieces, he cited conversations with ARM EVP Pete Hutton. In Microcontrollers Become Major at ARM (click here to read it), Hutton confirmed both the FD-SOI libraries and customers. In Cinderella (click here to read it), Manners looked at all the FD-SOI pieces – the recent Sony GPS presentation, involvement of players such as ARM, Samsung, Verisilicon, Open Silicon, Synopsys and Cadence – and concluded that, “Cinderella is finally going to the ball.”Posted February 17, 2015 - Share this Buzz
SemiWiki blogger Paul McLellan has posted another excellent FD-SOI piece, this time covering Samsung’s presentation at the recent FD-SOI/RF-SOI Workshop in Tokyo (click here to read it). Within 24 hours of posting, it had already been shared over 60 times on LinkedIn. As always, McLellan puts the presentation in perspective for the design community, calling out key highlights.Posted February 9, 2015 - Share this Buzz
A video made during ST’s FD-SOI presentation at IP-SoC 2014 has now been posted by designreuse on YouTube (you can see it here). Over 40 minutes long, it details the European THINGS2DO project, which includes almost 50 partners working on the FD-SOI ecosystem. (This follows onto the PLACES2BE project, which is finishing up this year.) It underscores the point that the markets for this ecosystem are very fragmented, so it’s critical that such an undertaking be as broad as possible.Posted February 9, 2015 - Share this Buzz
In a SemiEngineering piece entitled FD-SOI meets the IoT, Executive Editor Ann Steffora Mutschler talked to a couple of design houses working on FD-SOI IoT projects. Synapse Design has taped out multiple chips, and has more projects underway, they told her, with reports of impressive power savings. In close collaboration with a foundry, OpenSilicon is working on an FD-SOI test chip that should tape out soon. STMicroelectronics indicates that silicon-proven IP is now available through a reseller/IP vendor, and that digital-analog integration benefits are especially compelling. Mutschler also talked to Sonics, Semico, and the big EDA players. (Click here to read the article.)Posted February 8, 2015 - Share this Buzz
Peregrine Semiconductor has unveiled the UltraCMOS® PE42524, the industry’s first RF-SOI switch to operate up to 40 GHz (click here for product details, and here for the press release). This switch significantly extends Peregrine’s high-frequency portfolio into frequencies previously dominated by gallium arsenide (GaAs) technology. “Our UltraCMOS technology enables our high-frequency components, such as the PE42524, to reach performance levels previously considered unattainable in RF-SOI,” explains Kinana Hussain, senior marketing manager. “With a product roadmap that includes additional high-frequency components, Peregrine has, and will continue to, set new standards for RF-SOI.” As an alternative to GaAs-based solutions, the PE42524 features high reliability and performance advantages in linearity, isolation, settling time and ESD protection. These attributes make the switch ideal for test-and-measurement, microwave-backhaul, radar and military communications devices. Click here to see the video on YouTube. Click here to see more ASN articles about Peregrine’s RF-SOI.Posted February 8, 2015 - Share this Buzz
A new EETimes article entitled Sony Joins FD-SOI Club by Chief International Correspondent Junko Yoshida has created a tremendous buzz (click here to read it). The piece covers Sony’s presentation at the latest RF/FD-SOI workshop in Tokyo (many of the presentation are now posted here). Sony described their design experience with porting a GPS chip to 28nm FD-SOI, which resulted in a whopping 10x power reduction, down to just 1mW. Already the world’s smallest, lowest-power chip, the move to FD-SOI gives it a huge edge in mobile IoT and wearables, where battery life is critical. The response to the EETimes article was phenomenal. Within the first couple of days, it already had been shared over 90 times on LinkedIn and 50 on Facebook and Twitter.Posted February 2, 2015 - Share this Buzz
The recently announced IBM z13, which is billed as the world’s fastest microprocessor, is built on SOI (of course!) (read the press release here).
At the heart of the latest in the IBM z-series of mainframes, the chip is manufactured in 22nm SOI (partially depleted). IBM says it is 2X faster than the most common server processors, has 300 percent more memory, 100 percent more bandwidth and vector processing analytics to speed mobile transactions. As one of the most sophisticated computer systems ever built, the z13 is the first system able to process 2.5 billion transactions a day, enabling transaction analysis in “real time” to help prevent fraud as it is occurring, allowing financial institutions to halt the transaction before the consumer is impacted.
IBM says the z13 lowers the cost of running cloud. For compared environments, it is estimated that a z Systems cloud on a z13 will have a 32 percent lower total cost of ownership over three years than an x86 cloud and a 60 percent lower total cost of ownership over three years than a public cloud.
The z-series has been on SOI since it first launched in 2003.Posted February 2, 2015 - Share this Buzz
Leti’s monolithic 3D technology, which has now been dubbed “CoolCube”, was featured in a recent EETimes piece. Entitled True 3D monolithic integration eliminates TSV dependence (click here to read it), the article covers a Leti paper presented during a 3D-VLSI workshop preceding IEDM ’14. Leti’s Advanced CMOS lab manager Maud Vinet detailed the “cool” process in an FPGA, stacking a 14nm FD-SOI logic layer on top of a memory layer. It eliminates the need for TSVs, shrinks area by 55%, cut power in half and increases speed by 30%, effectively gaining a full node in terms of power and performance.Posted January 22, 2015 - Share this Buzz
Paul Boudre has been named CEO of SOI wafer leader, Soitec (see financial press release here). The company also announced its plans to re-focus on its core electronics business unit.
Q3 sales were 48 million euros, up 45% over last year. The sale of 200mm wafers (which are used in chips for RF-SOI and smartpower) were almost doubled from last year, and now represent three quarters of the company’s wafer sales. 300mm wafers (which are used for partially and fully-depleted SOI logic) were up by 16%. The company expects to see the ramp for 300mm FD-SOI wafers in H2 2015.
Boudre joined Soitec from KLA-Tencor in 2007. He has served as the company’s COO since 2008. He now takes over the CEO role from the company’s founder, André-Jacques Auberton-Hervé, who will continue as Chairman of the Board.
Soitec is restructuring its solar business and implementing cost-cutting measures.Posted January 22, 2015 - Share this Buzz
A new interactive WebEx webinar on FD-SOI design sponsored by CMC Microsystems has been posted. Entitled Design and Characterization of Circuits and Devices in the ST 28nm Fully-Depleted Silicon-On-Insulator (FD SOI) (click here to view it), it features two presentations by University of Toronto professors based on their recent experiences with circuit design in the ST’s 28nm FDSOI CMOS technology. The webinar provides insights about circuit design, the technology’s unique features and capabilities, test devices measurement results relative to other technologies, and explores how this technology can be used in mm-wave, high-speed digital and silicon photonics applications.
Two mixed-signal transceivers implemented in ST’s 28nm FDSOI CMOS technology targeting these applications are summarized. First, a low-power small-area transceiver compatible with the dense packaging technologies, such as silicon interposers, and operating up to 30Gb/s is presented. Second, a 20Gb/s wireline receiver including a decision feedback equalizer (DFE) with digital adaptation logic and a digital CDR are required. Both designs include both high-speed analog blocks and synthesized digital logic using the technology’s standard cell libraries.
The webinar lasts about an hour all told, with 5-minute Q&A sessions following each presentation. In the first minute or so there are a few technical snafus, but those are quickly resolved, so be patient: it’s worth the wait.Posted January 12, 2015 - Share this Buzz
A new world record of 46% for the direct conversion of sunlight into electricity was recently established by Soitec, Leti and the Fraunhofer Institute for Solar Energy Systems ISE (read the press release here). Multi-junction cells are used in concentrator photovoltaic (CPV) systems to produce low-cost electricity in photovoltaic power plants, in regions with a large amount of direct solar radiation.
Multi-junction solar cells are based on a selection of III-V compound semiconductor materials. The world record cell is a four-junction cell, and each of its sub-cells converts precisely one quarter of the incoming photons in the wavelength range between 300 and 1750 nm into electricity. When applied in concentrator PV, a very small cell is used with a Fresnel lens, which concentrates the sunlight onto the cell. The new record 46.0% efficiency was measured at a concentration of 508 suns and has been confirmed by the Japanese AIST.
Jocelyne Wasselin, Vice President Solar Cell Product Development for Soitec, predicts that they’ll reach the holy grail of 50% efficiency in the near future.Posted January 12, 2015 - Share this Buzz
The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) has issued the 2015 Call for Papers.
Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco, October 5-8. This industry-wide event will gather together widely known experts, contributed papers and invited talks on three main topics: SOI technology, subthreshold architectures with associated designs and 3D integration. With its 40-year history, the SOI segment continues as world’s premier conference to present and discuss state of the art SOI technical papers.Posted January 9, 2015 - Share this Buzz