Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
SOI wafer leader Soitec and SITRI (aka Shanghai Industrial µTechnology Research Institute) have announced a collaboration agreement. (Read the press release here.) They say the strategic partnership will strengthen their leadership in high-growth wireless communications and the global market for RF apps, with a special emphasis on the fast-developing Chinese RF ecosystem.
They’ll focus on developing RF-SOI using advanced circuit designs based on Soitec’s substrate materials and technologies.
“Experience shows that Soitec’s engineered substrates can optimize RF-SOI technology and applications in terms of both cost competitiveness and power efficiency. This strategic partnership will enable us to push the limits of RF circuits and meet future connectivity needs,” said Soitec CTO Carlos Mazure.
“Enhancing RF signal integrity is a key focus of the mobile communications industry as it builds toward 4G-LTE Advanced and 5G standards. We are excited to partner with Soitec in developing next-generation SOI communication solutions. It is consistent with SITRI’s mission to create a collaborative R&D and commercialization environment to catalyze the growth of advanced technologies,” said Dr. Charles Yang, president of SITRI.Posted June 12, 2015 - Share this Buzz
Silicon Europe (an alliance of Europe’s leading micro- and nanoelectronics clusters) and the SOI Consortium have organized an SOI Workshop on the 7th of July 2015, during the 10th Silicon Saxony Day in Dresden.
Here’s the agenda:
- Quick Introduction
- More than Moore Market Analysis and Opportunities (Yole)
- Power SOI and applications (NXP)
- Foundry offer (GlobalFoundries)
- FD-SOI status review (Giorgio Cesana, SOI Consortium)
- Analog/RF, sensors and MEMS in SOI: demos and performance assessment (Denis Flandre, UCL)
- Automotive IC needs (Infineon)
The workshop, which runs from 1:30 – 4:30, will be held in English. There is an entry fee (waived for students) for Silicon Saxony Day, but once you’re in, the SOI Workshop is free.Posted June 12, 2015 - Share this Buzz
CEA-Leti, a leading global center for applied research in microelectronics, nanotechnologies and integrated systems, is proudly hosting its 17th LetiDays in Grenoble on June 24–25, 2015, and associated seminars and workshops on June 22nd, 23rd and 26th (click here to go to the registration site).
On June 22-23, Leti will present their first workshop on FD-SOI. This Forum brings together a stellar line-up from academia, semiconductor companies, system design houses and the EDA industry to build a vision of the strategic directions and state-of-the-art in FDSOI IC design. Click here to see the schedule – it’s impressive.
The big themes for this year’s Leti Days are Internet of Things-augmented mobility, and managing connected devices and the services and apps they offer. This also gives Leti a chance to show off their remarkable array of technological breakthroughs in silicon technologies, sensors, telecommunications, power management in wearable systems, health applications, the transport market up to the factory and cities of the future.
The event will feature 40+ conferences, many networking opportunities, a showroom and exhibition halls. You’ll hear and meet market leaders, startups, analysts and Leti technology experts. As with every Leti Days event, you’ll get a comprehensive vision of the latest innovations in key technologies and markets, and be provided with opportunities to complement your roadmaps with Leti expertise.
If you can’t make it to Grenoble, watch for other Leti Days coming up in San Francisco during Semicon West and in Tokyo, among others.Posted May 29, 2015 - Share this Buzz
RF-SOI specialist Peregrine continues to expand its “SOI University” series of webinars (click here to see the full offering), which has been ongoing for five years now. The latest webinar (the fifteenth in the series) is entitled, Linearity: The Key to Successful Data Transmission in Cable & Beyond. It is presented by Peter Bacon, the company’s Director of System Integration. In this 48-minute webinar, Peter explains how data rates have continued to increase in virtually every application. As an example, he discusses DOCSIS 3.1 and explains that linearity is an essential factor in meeting the new requirements. Finally, he describes the benefits of Peregrine’s UltraCMOS® technology in meeting these requirements.Posted May 29, 2015 - Share this Buzz
For the first time, IBM engineers have designed and tested a fully integrated wavelength multiplexed silicon photonics chip, which the company says will soon enable manufacturing of 100 Gb/s optical transceivers (read the press release here). This will allow datacenters to offer greater data rates and bandwidth for cloud computing and Big Data applications.
Early in the program (back in 2007), IBM contributed a piece to ASN about why their photonics program is on SOI – you can read that here. (Most all photonics — except the lasers — are on SOI. You can read more ASN photonics pieces from Intel and others here.)
Silicon photonics greatly reduces data bottlenecks inside of systems and between computing components, improving response times and delivering faster insights from Big Data. IBM’s breakthrough enables the integration of different optical components side-by-side with electrical circuits on a single silicon chip using sub-100nm semiconductor technology.
IBM’s silicon photonics chips uses four distinct colors of light travelling within an optical fiber, rather than traditional copper wiring, to transmit data in and around a computing system. In just one second, this new transceiver is estimated to be capable of digitally sharing 63 million tweets or six million images, or downloading an entire high-definition digital movie in just two seconds.
IBM presented details at the recent 2015 Conference on Lasers and Electro Optics.Posted May 14, 2015 - Share this Buzz
International research teams working on or interested in the far-reaching SOIPIX radiation-detector project have a workshop coming up in June. The project was originally started by KEK* scientists to develop a new detector technology and quantum beam imaging for high-energy particle physics. As research teams around the world (including Japan, USA, China and Europe) joined to take advantage of the multi-wafer project runs, it soon expanded to include more applications. (To learn more about the program, click here.)
Leveraging the SOIPIX strategy of SOI-based monolithic sensor-electronics integration, applications are now being developed in areas such as medical (x-ray sensors and radiotherapeutic systems), materials research, nuclear physics, astrophysics, electron microscopy and industrial uses (such as x-ray inspection systems).
(Here at ASN, we covered the project and its implications for medical imaging back in 2010 – click here to read that piece.)
The next workshop, SOIPIX2015, will take place at Tohoku University (Sendai, Japan) 3-5 June 2015. Registration has been extended until 22 May 2015. Click here for registration information.
*KEK is Japan’s High Energy Accelerator Research Organization.Posted May 14, 2015 - Share this Buzz
A recent GlobalFoundries blog entitled RF-SOI is IoT’s Future, and the Future is Bright (read it here) says, “RF SOI is a win-win technology option that can improve performance and data speed in smartphones and tablets, and it is expected to play a key role in the Internet of Things applications as well.”
The blog touches on the full range of benefits of RF-SOI for front-end integration, resulting in, “… longer battery life, less dropped calls and higher data speeds.” It then goes on to cite complementary advantages of FD-SOI. Peter Rabbeni, GlobalFoundries director of RF Segment Marketing, notes that in FD-SOI, “dynamic control of Vdd and the use of well-bias techniques can not only help reduce overall power consumption but can be used as a means to optimize RF circuit operation. This is not something that can be easily done in bulk technologies.”Posted April 30, 2015 - Share this Buzz
Presentations given at the ‘Beyond Computing’ Innovative Technologies Symposium (March 2015 in Shanghai) are now available on the SOI Consortium website (click here to see the list). The Symposium covered MEMS, semiconductor manufacturing, RF and power, which are key topics for the fast growing “More than Moore” industry. The one-day, closed-door symposium was organized by members of the SOI Consortium and the Shanghai Industrial μTechnology Research Institute (SITRI) to facilitate exchanges with industry leaders in China.Posted April 30, 2015 - Share this Buzz
RF-SOI will play a key role in the IoT plans of analog and mixed-signal specialist MagnaChip (read the press release here). The company has launched a task force to address IoT. The statement says, “MagnaChip also offers 0.18 micron and plans to offer 0.13 micron Silicon on Insulator (SOI) RF-CMOS technologies, which is suitable for use in antenna switching, tuner and Power Amplifier (PA) applications. Switches and tuners are core components of wireless Front-End-Modules (FEMs) for cellular and Wi-Fi connectivity in IoT devices. MagnaChip’s CMOS based FEMs reduce manufacturing cost and time to market while providing competitive performance for multiband and multimode smartphones, tablets and other IoT devices.”
Commenting on the IoT opportunity, YJ Kim, MagnaChip’s interim Chief Executive Officer, said, “We believe there is tremendous growth opportunity in the IoT market and our participation is part of our overall strategy to broaden our product portfolio in new markets. MagnaChip’s IoT task force and business consortium with key business partners will reinforce our position as a key manufacturing service provider in the expanding IoT market.”Posted April 27, 2015 - Share this Buzz
Research and consulting group Semico has issued a new report entitled SOI Update 2015: Finding New Applications (for information on getting a copy of the report, click here). As described on the Semico website: “With the recent growth in RF-SOI for switches and integrated solutions for RF functions such as power amplifiers and transceivers, the opportunities for growth in SOI wafer demand have once again garnered a lot of attention. In addition, as the industry transitions to very complex and expensive finFET technology, SOI is providing a high performance, low power option to semiconductor vendors who do not want take on the challenges of finFETs. This report explores the markets, products and outlook for SOI wafer adoption over the next five years.”Posted April 27, 2015 - Share this Buzz
Right on schedule, the SFARDS cryptocurrency ASIC on 28nm FD-SOI has made its debut in silicon, and is surpassing expectations. In what is clearly a stunning success, the company announced that the ASIC’s lowest working voltage is 0.45V. This means it operates stably at a power supply voltage that’s about half that of competing 28nm offerings.
An article published on the SFARDS website (see the whole thing here) said, “Using the latest in FD-SOI processing technology, SFARDS has successfully completed its 28nm SF3301 dual-algorithm ASIC chip. The SF3301 is the world’s first chip to use this manufacturing process and is at the same time the world’s first 28nm dual-algorithm (SHA-256 & Scrypt) chip, capable of mining these two algorithms simultaneously or singularly.
“SFARDS’ SF3301 fully utilizes the advantages of the FD-SOI technology. This brings increased forward body bias; the chip is operational at lower voltage while maintaining a higher frequency. The chip boasts impressive power efficiency while affording high hash power, allowing for much lower wastage per hash. The ASIC’s lowest working voltage is 0.45V.”
As noted in ASN’s Buzz in March 2015 (read it here), cryptocurrency (the best-known example of which is Bitcoin) depends on “ledgers” supported by bitcoin “mining” chips. As well-explained in an arstechnica piece (read it here), while some Bitcoin mining is done on CPUs and GPUs, serious mining requires much faster and lower power ASICs in the hardware.Posted April 21, 2015 - Share this Buzz
CEA-Leti’s newest version of its advanced compact model for FD-SOI is now available in all major SPICE simulators (get the press release here). The Leti-UTSOI2.1 is the latest version of Leti’s compact model for FD-SOI, which was first released in 2013. (Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. )
Leti-UTSOI2.1 further improves predictability and accuracy. These improvements include a direct and predictive link between bi-dimensional device electrostatics and process parameters, a refined description of narrow-channel effects, improved accuracy of moderate inversion regime and gate tunneling current modeling.
“This new version of the ultra-thin SOI model, which affirms Leti’s continuing leadership in FD-SOI technology, is ideal for designers seeking differentiation in energy management and performance for advanced nodes,” said Leti CEO Marie-Noëlle Semeria
Leti-UTSOI2.1, which considerably extends the domain of physical device description compared to other solutions, is now available in most of the commercial SPICE and Fast SPICE simulators used by industry.Posted April 21, 2015 - Share this Buzz
In a new YouTube video, Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI, especially for ultra-low-power, IoT, wearables, networking and automotive apps. The five-minute video was taped by ChipEstimate.TV host Sean O’Kane during the Cadence User Conference (CDNLive, Silicon Valley, March 2015 – click here to see it). While the first half addresses 14nm FinFET, starting at the 2:25 mark, it’s all about FD-SOI.
First Kelvin reminds viewers that 28nm will be a long-lived node thanks to its lower costs and the fact that it doesn’t use double patterning. He says Samsung has acquired a number of customers for FD-SOI, and now has the complete ecosystem to support the process technology, from substrate suppliers through the design chain. The key value, he says, is in the extremely low power operation and the low power supply voltage, which translates into long battery life for IoT and wearables. He also says he’s very excited by the prospects for FD-SOI in the automotive domain, where it is especially valued for its enhanced reliability.Posted April 9, 2015 - Share this Buzz
Hua Hong Semiconductor of Shanghai (a pure-play 200mm foundry operated by HHGrace Semi) recently launched a 0.2μm RF-SOI process design kit (PDK) (click here to read the full press release). The 0.2μm RF-SOI technology platform has been successfully validated and is ready for customers product design and development, says the company. It is tailored and optimized for wireless RF front-end switch applications. The new PDK solution is developed from Cadence’ IC5141 EDA software, and integrates RF modeling and simulation platform such as PSP SOI and BSIM SOI. The company notes that the 0.2μm RF-SOI PDK offering provides convenience to designers who focus on optimizing both the RF performance and die size, while greatly shortening time-to-market.
Dr. Weiran Kong, Executive Vice President of Hua Hong Semiconductor said, “With the booming of mobile Internet and intelligent terminals in recent years, there are more and more applications of consumer electronics with the use of RF SOI design. 0.2μm RF-SOI technology is one of our focuses. With this new offering, we will actively help our customers to capture market opportunities. The technology is ideal for RF switch designs such as smartphones and connected devices of Internet of Things. Through adding 0.2μm RF SOI technology solution into our RF portfolio, we are able to provide customers with comprehensive, cost effective and high performance RF solutions, which also include RF CMOS, SiGe BiCMOS and embedded Flash technology with RF PDK.”
The Group currently has one of the largest 200mm wafer processing capacities in China through its three fabs in Shanghai, with an approximate total 200mm wafer manufacturing capacity of 129,000 wafers per month as of September 30, 2014.Posted April 9, 2015 - Share this Buzz
The Heterogeneous Technology Alliance (HTA), a coalition of top European R&D organizations, is offering an SOI-MEMS platform. Looking to bridge the gap between academia and industry, this technological platform pools the SOI-MEMS expertise, capabilities and fabrication facilities of Leti (France), Fraunhofer (Germany), CSEM (Switzerland) and VTT (Finland).
The main focus of HTA (click here for the website) is the further development of innovative Smart Systems. SOI-MEMS is typically used for silicon oscillators, microphones, speakers, compass, navigation, motion sensors, sensors and actuators, energy harvesting, micro fuel cells, microfluidics and other deep reactive-ion etched micro structures. A recently issued brochure gives an overview of the offering.
The HTA is active at all levels of Smart Integrated Systems Solutions: from applied research on materials, processes and equipment through the fabrication of devices and components to the development of new products and services. Development and small-scale production cleanrooms for micro-electronics, MEMS, power electronics and analogue components is available. Wafer handling capacity encompasses wafer sizes ranging from 100, through 150 and 200 to 300 mm.
A one-stop shop for complete system solutions, the HTA guarantees simple access to an enlarged portfolio of technologies and is structured to facilitate technology transfer to European and non-European companies. In addition to working with large industrial partners, the HTA offers services specially suited for small and medium-sized companies. With a combined staff of more than 5,000 scientists and a portfolio of more than 3,000 patents, the HTA is de facto the largest European organization in the field.Posted March 27, 2015 - Share this Buzz