Wondering what’s new, what’s hot and what’s next in the SOI and advanced substrate world? Check
out our Industry Buzz – now featuring regular updates.
American Semiconductor has announced the FleX-MCU™ product family. Leveraging an SOI starting wafer, the FleX-MCU is the world’s first physically flexible microcontroller fabricated using the FleX™ Silicon-on-Polymer™ process. The FleX-MCU is an 8-bit RISC microcontroller with 8KB embedded RAM operating up to 20MHz, and is the initial product for a full portfolio of physically flexible ICs. The FleX IC roadmap includes microcontrollers, analog-to-digital converters (ADC), radio frequency (RF) wireless communications, and non-volatile memory (NVM).
“The Silicon-on-Polymer process can be applied to a variety of standard SOI wafers from any commercial wafer foundry or IDM. The FleX-MCU demonstrates a standard foundry process used to develop physically flexible FleX ICs. This means customers can create their own custom FleX ICs in addition to using our catalog products,” said Rich Chaney, General Manager of American Semiconductor
The FleX-MCU is fabricated in TowerJazz Semiconductor’s CS13 process. The CS13 PDK can be used to design flexible ICs; the IP blocks used in the FleX-MCU are available from American Semiconductor for customers to include in their custom designs.
In a previous announcement, Dr. Marco Racanelli, Sr. Vice President of TowerJazz said, “FleX is a post-fabrication process that can be applied to our production SOI technology making it possible to turn any product into a flexible die helping our customers create new, differentiated solutions. We are excited to partner with American Semiconductor and look forward to jointly participate in the growth of this new market.”Posted June 17, 2013 - Share this Buzz
Soitec has announced the industry’s first four-junction solar cell for concentrator photovoltaic (CPV) systems, entering the industry’s roadmap at a world-class level with 43.6 % efficiency. Soitec is best known as the world’s leading producer of SOI wafers for microelectronics. For the new generation of optimized III-V-based multi-junction solar cells, Soitec has leveraged its proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies and collaborated with Fraunhofer and Leti.
Soitec’s CPV modules are built on Concentrix technology, using Fresnel lenses to concentrate sunlight 500 times and focus it onto the tiny, highly-efficient multi-junction solar cells. Different types of solar cells are stacked on top of one another, with each cell type designed to convert a certain range of the solar spectrum: short wave radiation, medium wave radiation and infrared. The current generation of this technology is triple junction, achieving module efficiency of 30% — almost twice as high as the efficiency of conventional silicon photovoltaic modules.
To reach 43.6 % efficiency, Soitec’s innovative new four-junction cell uses two new, highly sophisticated dual-junction sub cells grown on different III-V compound materials, which allows optimal band-gap combinations tailored to capture a broader range of the solar spectrum. This maximizes energy-generating efficiency, and puts the company on track to be the first to reach the target of a 50% cell efficiency level.Posted June 10, 2013 - Share this Buzz
SOI and other advanced substrate based technologies will be significant beneficiaries of the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In addition to the recently announced €360M FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe), other projects announced by the ENIAC JU* include:
- E450EDL (“European 450mm Equipment Demo Line”, €205.7M, 43 members) – this project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition.
- AGATE (“Development of Advanced GaN substrates & Technologies”, €59.6M, 10 members, lead by Soitec) The project plans to set-up three pilot lines for GaN-based advanced substrates and devices to help the introduction and market acceptance of these More-Than-Moore technologies.
- Lab4MEMS (“LAB FAB for smart sensors and actuators MEMS”, €28.5M, 21 members, lead by ST) aims to establish a European Pilot Line targeting the market drivers in consumer and healthcare application such as body area sensors and remote monitoring.
As European Commission Vice President Neelie Kroes said, “I want to double our chip production to around 20% of global production. [...] It’s a realistic goal if we channel our investments properly.”
*The ENIAC Joint Undertaking (JU) is a public-private partnership focusing on nanoelectronics that brings together ENIAC Member/Associated States, the European Commission, and AENEAS (an association representing European R&D actors in this field). The document providing details on the pilot line projects is available here.Posted June 6, 2013 - Share this Buzz
In the three months following Peregrine Semi’s announcement of the latest version of its UltraCMOS® process technology, STeP8 for RF Front End ICs, the company has followed with a steady stream of news. (The UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec.) Recent announcements include:
- a collaborative sourcing and UltraCMOS® license agreement with Murata;
- four new DuNE™ Digitally Tunable Capacitors (DTCs), creating the industry’s broadest integrated RF tuning IC portfolio;
- an agreement with Taoglas to bring a dynamically tunable LTE antenna solution to the machine-to-machine (M2M) market;
- a new SPDT RF switch for harsh environment and space applications;
- the industry’s highest-isolation SPDT RF switch for the wireless infrastructure market;
- an AEC-Q100 Certified SPDT RF switch for harsh environment automotive designs;
- UltraCMOS® RFICs are in Globalstar Communication Satellites.
Chipworks’ teardown guru Dick James (@ChipworksDick) recently Tweeted that Peregrine has two switches in Samsung’s Galaxy S4.Posted May 31, 2013 - Share this Buzz
Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array control and sensing scheme, which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models, sureCore has designed an SRAM memory consuming less than half the power of existing solutions. SureCore is working closely with Gold Standard Simulations (GSS) Ltd. (GSS Founder/CEO Asen Asenov is a sureCore director).Posted May 31, 2013 - Share this Buzz
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs. The partnership gives MOSIS’ customers access to imec’s state-of-the-art fully integrated silicon photonics processes and Tyndall’s advanced silicon photonics packaging technology. Co-founded by Leti and imec in 2009, ePIXfab offers a cost-effective way for researchers and small and medium sized companies to prototype photonic integrated circuits on SOI.Posted May 23, 2013 - Share this Buzz
Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.” One of the industry’s most prestigious, the Grove Award is sponsored by the IEEE Electron Devices Society, recognizing “outstanding contributions to solid-state devices and technology.” As noted in the EDS Newsletter, Dr. Colinge’s “…strong actions and enthusiastic beliefs were crucial for supporting the development of SOI technology.” One of the giants of the SOI community, Dr. Colinge is especially heralded in the industry for his seminal and continued work in multigate FETS (aka MuGFETs, a category that includes architectures such as FinFET and TriGate among others). Dr. Colinge and his work have been featured in many editions of ASN. Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).Posted May 23, 2013 - Share this Buzz
The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost. A new 3-year public-private project involving 500 engineers from 19 members in seven countries is looking to enable volume manufacturing in Europe from 28nm down to 10nm. The Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL.
SiTime, which leverages SOI for high-performance MEMS timing solutions, has entered the smartphone/tablet/mobile app market with the first MEMS oscillator in a chip scale package (CSP). SiTime’s solutions offer area savings of 85%, cut power by 50% and are 15 times more reliable, all of which enable smaller, lower power and longer lasting mobile electronics. SiTime already claims 80% share of the MEMS timing market. The new SiT15xx family of 32 kHz MEMS oscillators can replace crystal resonators in mobile apps, eliminating the need for load capacitors, minimizing board area and also offers a more robust system startup in extreme temperatures, says the company. In addition to smartphones and tablets, the SiT15xx family is ideal for devices that require small size and low power such as fitness monitoring and watch products, medical monitoring and wellness devices, sport camcorders, wireless keypads and mouse devices. Devices in the chip scale package begin sampling in May 2013.Posted May 10, 2013 - Share this Buzz
An agreement between Soitec and GT Advanced Technologies is aiming to lower the cost of LED production and accelerate adoption in commercial and residential lighting. GT is developing an HVPE (high productivity hydride vapor phase epitaxy) system incorporating Soitec Phoenix Labs’ (a subsidiary of Soitec) unique and proprietary HVPE technology. This includes Soitec’s novel and advanced source delivery system that is expected to lower the costs of precursors delivered to the HVPE reactor. The HVPE system will enable the production of GaN template sapphire substrates at scale. The expected target date for the commercial availability of the HVPE system is the second half of 2014.Posted May 6, 2013 - Share this Buzz
Soitec‘s Smart Cut™ technology, best known for its role as the leading technology for producing SOI wafers, is now being leveraged to produce GaN substrates for high-performance LED lighting applications. Following a successful pilot line announced last year, Sumitomo Electric will now industrialize the product and invest in Smart Cut technology. Yoshiki Miura, general manager of the Compound Semiconductor Materials Division at Sumitomo Electric, said, “By combining the two innovative technologies – Soitec’s Smart Cut technology and our high-quality, large-diameter, free-standing GaN substrates – we are able to offer a high-value proposition to our LED customers. Soitec’s unique material-transfer technology enables the reuse of GaN wafers several times, achieving a substantial reduction in the cost of high-quality GaN materials to serve high-volume applications.”Posted May 6, 2013 - Share this Buzz
On April 22, 2013, leading companies from the SOI Industry Consortium organized a forum focused on fully depleted technologies for highly energy-efficient System-on-Chip applications.
This forum was co-organized by Horacio Mendez from the SOI Consortium, Gary Patton from IBM and Mike Noonen from GLOBALFOUNDRIES.
The presentations are now posted on the SOI Industry Consortium website:
This includes slides from the big 3 SOI wafer suppliers (SEH, Soitec and SunEdison (formerly MEMC)), market projections by analyst group IBS, technical analysis by PDF Solutions, STM on migration to 28nm FD-SOI, SOCs on FD-SOI by GlobalFoundries, and IBM on SOI-FinFETs.
DARPA reports that a team of researchers at the University of Southern California and Columbia University has achieved output power levels of nearly 0.5W at 45 GHz with a 45nm SOI CMOS chip. This world record result for CMOS-based power amplifiers doubles output power compared to the next best reported CMOS millimeter-wave power amplifier. The chip design used multiple stacked 45nm SOI CMOS devices for increased effective output voltage swing and efficient 8-way on-chip power-combining. Results will be reported at the 2013 Institute of Electrical and Electronics Engineers Radio Frequency Integrated Circuits Symposium. RF power amplifiers are used in communications and sensor systems for next-generation military microsystems in areas such as radar, guidance and high data rate communications to boost power levels for reliable transmission of signals over the distance required by the given application. These breakthroughs were achieved under the Efficient Linearized All-Silicon Transmitter ICs (ELASTx) program.Posted April 12, 2013 - Share this Buzz
Specialty foundry Altis Semiconductor will be a foundry partner for the IBM 180nm SOI technology. ALTIS will deliver high volume products starting Q2 2013 and will secure capacity increase for 2014 and beyond to address the IBM forecasted demand. This foundry agreement addresses the next generation of consumer products, including as an example, the RF/SOI chipsets used in the world most advanced mobile devices. IBM’s 7RFSOI technology provides advantage by simultaneously enabling the required level of integration and performance for the large number of switches required in the modern smartphone for example cellular antenna switches, diversity antenna and WLAN, says the company.Posted March 18, 2013 - Share this Buzz
Peregrine has announced the latest version of UltraCMOS® process technology—Semiconductor Technology Platform 8 (STeP8), which the company says enables unmatched performance in RF Front End ICs. STeP8 technology shows a 36% improvement in Ron Coff performance over STeP5 technology announced just one year ago—dramatically improving the linearity, insertion loss, and isolation capabilities of Peregrine’s RFIC products. The UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec. For challenges such as the LTE environment, UltraCMOS STeP8 enables mobile wireless device designers to incorporate high performance components into the RF Front End while maintaining a small form factor and consistent, reliable operation, says the company. It is leveraged in Peregrine’s expanded DuNE™ Digitally Tunable Capacitor (DTC ) product line with six second-generation devices for antenna tuning in 4G LTE smartphones.Posted March 18, 2013 - Share this Buzz