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CONFERENCE PROCEEDINGS

IEDM

http://www.his.com/~iedm/

San Francisco, December 2008

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here is a comprehensive listing of the papers of interest to the SOI and advanced substrates community.

• Comprehensive Study on V_th Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation.  N. Sugii, et al.  (Hitachi)
  Silicon on Thin BOX (SOTB) for high-speed, low-power SOCs has the smallest V_th variation among all planar CMOS structures.  Researchers have now found ways to reduce threshold voltage variation even further.  (Read the full story in ASN#12)
• High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding.  O. Weber, et al. (Leti/ST/Soitec)
  Undoped FD-SOI architectures are extremely effective in controlling V_t variability.  Variation in the thickness of the top silicon is found not to be a significant factor in V_t variation; rather, thinning the top silicon minimizes V_t fluctuations.  (Read the full story in ASN#12)
• 22 nm Technology Compatible Fully Functional 0.1 µm2 6T-SRAM Cell.  B. S. Haran, et al. (IBM/Freescale/AMD) 
  Researchers from the IBM Alliance describe the world’s smallest fully functional SRAM memory cell. This work suggests that SRAM technology can be extended on planar SOI.
• Autonomous Refresh of Floating Body Cell (FBC).  T. Ohsawa, et al. (Toshiba)
  The physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without a sense amplifier operation. Therefore, FBC can be used to realize static RAM without periodical refresh while retaining data.
• First Observation Of Finfet Specific Mismatch Behavior And Optimization Guidelines For SRAM Scaling. T. Merelle, et al. (NXP/TSMC/IMEC)
  Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. This study provides guidelines for SRAM design in a FinFET technology.
• 190V N-Channel Lateral IGBT Integration in SOI 0.35µm BCD Technology.  M. Sambi, et al. (STMicroelectronics)
  The integration of 190V N-Ch. LIGBT in SOI 0.35μm shrunk BCD technology is described. The novel device shows a very high saturation current and good HTRB robustness.
• Implementation and Optimization of Asymmetric Transistors in Advanced SOI CMOS Technologies for High Performance Microprocessors.  J. Hoentschel, et al. (AMD/U.Dresden)
  Sub-40nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65nm and 45nm PD-SOI CMOS technologies. Product-level implementation shows a speed benefit of 12%.
• Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature.  J. Chen, et al. (U.Tokyo)
  Accurate electron mobility in nanowires on (110) SOI has been achieved by the split C-V method for the first time.
• Silicon Photonic Modulator and Integration for High-speed Applications. (Invited)  L. Liao, et al. (Intel/Numonyx)
  Researchers presented recent results of a silicon photonic integrated chip that is capable of transmitting data at an aggregate rate of 200 Gb/s. This is a continuation of the SOI-based work that Ansheng Liu of Intel wrote about in ASN8.
• Impact of SOI, Si1-xGexOI and GeOI Substrates on CMOS Compatible Tunnel FET Performance.  F. Mayer, et al (CEA-LETI)
  This paper reports on the first experimental investigations in SOI, Si1-xGexOI & GeOI Tunnel FET (TFET).  The devices were fabricated using a FD SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS.
• Improved Effective Switching Current (IEFF+) and Capacitance Methodology for CMOS Circuit Performance Prediction and Model-to-Hardware Correlation.  X. Yu, et al. (IBM)
  This paper demonstrates new effective drive current IEFF + methodologies to address predictability of circuit performance across wide V_t range and accuracy of effective resistance REFF prediction-to-hardware correlation.
• Setting up 3D Sequential Integration for Back-Illuminated CMOS Image Sensors with Highly Miniaturized Pixels with Low Temperature Fully Depleted SOI Transistors. P. Coudrain, et al. (STMicroelectronics, CEA LETI-MINATEC, Institut Superiéur de l'Aéronautique et de l'Espace)
  This paper presents an innovative 3D BSI architecture capable of overcoming pixel miniaturization drawbacks.
• On The Difference of Temperature Dependence of Metal Gate and Poly Gate SOI MOSFET Threshold Voltages.  S.-J. Han, et al. (IBM)
  The temperature dependence of device performance is a critical factor that determines overall product power-performance. The paper shows HKMG gate stacks drive significantly higher threshold temperature dependence over poly-Si/SiON. In SOI, the work-function engineering enabled by HKMG integration schemes can result in even higher Vt temperature sensitivity attributed to differences in floating body behavior. The combined effects result in higher drive current at elevated temperature.
• Gate Length Scaling and High Drive Currents Enabled for High Performance SOI Technology using High-k/Metal Gate.  K. Henson, et al. (IBM, Freescale, AMD)
  CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25nm, highlighting the scalability of this approach for high performance SOI CMOS technology.
• High Piezoelectric Properties In LiNbO3 Transferred Layer By The Smart Cut™ Technology For Ultra Wide Band BAW Filter Applications.  J.-S. Moulet, et al. (Soitec, Leti)
  For the first time, HBAR resonators based on monocrystalline films of LiNbO3 fabricated using the Smart Cut™ technology were processed and characterized between 1 and 4 GHz, with results far superior to those obtained with traditional AlN material. This confirms the interest of this technology for ultra wide band BAW filters.
• Experimental Study on Quasi-Ballistic Transport in Silicon Nanowire Transistors and the Impact of Self-Heating Effects.  R. Wang, et al. (Peking U., Samsung)
  This paper investigates ballistic efficiency and self-heating effects in GAA silicon nanowire transistors (SNWTs). It is experimentally found that, even if the SNWT is fabricated on bulk-Si substrate, the self-heating effect is worse than SOI devices.
• Demonstration of Highly Scaled FinFET SRAM Cells with High-k /Metal Gate and Investigation of Characteristic Variability for the 32 nm Node and Beyond.  H. Kawasaki, et al  (Toshiba, IBM, Freescale, AMD)
  Researchers fabricated highly scaled FinFET SRAM cells, with area down to 0.128 m2, using high-k dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, mainly caused by heavy doping into the channel region.
• Impact of Strain on ESD Robustness of FinFET Devices.  A. Griffoni, et al  (IMEC, U. Padova, Infineon, LAAS/CNRS, Texas Instruments)
  Researchers found that strain improves the ESD robustness up to 30% in multi-fin FinFETs. 
• Atomistic Modeling of Impurity Ion Implantation in Ultra-Thin-Body Si Devices.  L. Pelaz, et al  (U. Valladolid, NXP-TSMC, IMEC, Philips Research Labs)
  Source/drain formation in ultra-thin body devices by conventional ion implantation is analyzed using atomistic simulation. The conclusions of the atomistic modeling are verified by a novel characterization methodology and electrical analysis.
• Multi-Gate Vibrating-Body Field Effect Transistors (VB-FETs).  D. Grogg, et al (École Polytechnique Fédérale de Lausanne)
  This paper reports on the design, fabrication and detailed characteristics of multi-gate vibrating-body field effect t ransistors (VB-FETs).  For the first time, the researchers experimentally demonstrate an active MEM resonator concept, with built-in amplification, which has a negative resistance of -30 Ohms, enabling the possibility of building an oscillator without any sustaining amplifier, thus reducing the power consumption and oscillator size.
• Sub-20 nm Gate Length FinFET Design: Can High-k Spacers Make a Difference?  A.B. Sachid, et al (Indian Institute of Technology Bombay, Infineon)
  The authors present a novel device design methodology for the 45 nm technology node and below, for undoped underlapped FinFETs with high-kappa spacers to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped FinFETs.
• Transport-Based Dopant Metrology In Advanced FinFETs.  G.P. Lansbergen, et al (Delft TU, Purdue U., U. Melbourne, IMEC)
  Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. The authors correlated the impurity's chemical species and determined their concentration, local electric field and depth below the Si/SiO₂ interface, demonstrating a new approach to atomistic impurity metrology and confirming the assumption of tunneling through individual impurity quantum states.
• Novel Si-Based Nanowire Devices: Will they Serve Ultimate MOSFETs Scaling or Ultimate Hybrid Integration? (Invited)  T. Ernst, et al  (Leti)
  Since both CMOS scaling and NEMS sensor devices scaling converge to the same type of sub-100 nm objects, the authors explain how this opens the door to chips integrating both complex signal treatment and very highly sensitive sensing functionalities.
• 15nm-Diameter 3D Stacked Nanowires with Independent Gates Operation: ФFET.  C. Dupre, et al (Leti, IMEP-LAHC, INPG-MINATEC, STMicroelectronics)
  The authors report the first 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.
• Enhancing SRAM Cell Performance by Using Independent Double-Gate FinFET.  K. Endo, et al (National Institute of Advanced Industrial Science and Technology Tsukuba)
  The authors have successfully fabricated SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs and investigated the performance. They demonstrated both a reduction of leakage current and an enhancement of read and write noise margins.

SPIE Photonics West

http://spie.org/x33616.xml

San Jose, January 2009

SPIE Photonics West is North America's largest commercial exhibition on optics, lasers, biomedical optics, optoelectronic components, and imaging technologies.

• Luxtera won two top awards for its new, SOI-based  "Blazar" product: it was both the overall “Best In Show” and winner of the Photonics Systems category for the 2008 Prism Awards.  Luxtera was recognized for its ability to integrate high-performance optics directly with silicon electronics on a monolithic CMOS chip. In addition, Luxtera is the first company to deliver a commercial product, Blazar, based on its CMOS Photonic Intellectual Property.
  Blazar is a monolithic optoelectronic Optical Active Cable assembly containing four complete fiber optic transceivers per end, each operating at data rates from 1 to 10.5 Gbps and supporting a reach up to 300 meters. This integrated cable solution provides low cost reliable transport for aggregated data rates up to 40 Gbps (4X10 Gbps).
• Mario Paniccia, Intel Fellow and Director of Photonics Technology Labs, described breakthroughs in development of the ability to make optics in silicon photonics. This is a continuation of the SOI-based work described by Intel’s Ansheng Liu in ASN8.

Other papers at Photonics West:

• A high-sensitivity Hall sensor fabricated on a SOI wafer using surface micromachining technique.  Namit Singh, et al (U. North Carolina)
• Integrated position sensing for 2D microscanning mirrors using the SOI-device layer as the piezoresistive mechanical-elastic transformer.  Jan Grahmann, et al. (Fraunhofer)
• 1 mm by 1 mm SOI etched diffraction grating with 0.5 micron waveguide aperture and 0.62 nm channel spacing.  Yingyan Huang, et al. (OptoNet, Northwestern U.)
• The design of signal processing devices employing SOI-MMI couplers.  Laurence W. Cahill, et al. (La Trobe U.)

EuroSOI 2009

http://chalmers2009.eurosoi.org/

Chalmers University, Sweden, January 2009

EuroSOI is an international forum to promote interaction and exchanges between research groups and industrial partners involved in SOI activities all over the world.

• SOI vs. Bulk.Si nanoscale FinFET’s. (Invited)  J. G. Fossum, et al. (U. Florida/Gainesville, Applied Novel Devices, Soitec)
• Platforms for planar & non-planar ultrathin silicon.  M. Schmidt, et al. (AMO, RWTH)
• Junctionless MuGFETS.  C.-W. Lee, et al. (Tyndall)
• Strain induced enhancement of transconductance in Si-nanowire transistors fabricated by pattern dependent oxidation.  D. Kosemura1, et al. (Meiji U., Waseda U.)
• Floating-Body-Effect-Related Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device.  H. J. Hung1, et al. (National Taiwan U., UMC)
• Thin film devices for low power applications. (Invited)  S.Monfray, et al. (STMicroelectronics, Leti)
• Ultra-thin body and BOX SOI roadmap for low power and low VT-variability MOSFETs.  P. Scheiblin, et al. (Leti, Soitec)
• Transconductance and mobility behaviors in UTB SOI MOSFETs with standard and thin BOX.  T. Rudenko, et al.  (NAS/Ukraine, UCL, Leti, Soitec)

International Solid-State Circuits Conference (ISSCC)

http://www.isscc.org/isscc/index.htm

San Franciso, February 2009

ISSCC is the foremost forum for presentation of advances in solid-state circuits and systems-on-a-chip.

• A 4-Side Tileable Back-Illuminated 3D-Integrated Mpixel CMOS Image Sensor.  V. Suntharalingam, et al.  (MIT Lincoln Labs, Irvine Sensors, Forza Silicon)
  The paper presents a 3D-integrated back-illuminated (BSI) 1Mpixel CMOS image sensor tile for surveillance and astronomy.  It includes a stack of 2x32-channel vertically integrated ADC chips, and requires 13.4μm of silicon perimeter to the pixel array. The tile and system connector design supports 4-side abuttability and burst data rates of 1Mpixel in 1ms. The first layer of the 3D-integrated 1Mpixel CMOS image sensor has photodiodes with 100% fill factor and is connected to a second layer consisting of SOI-CMOS pixel readout and selection circuitry. The next layers provide the digital system interface and serve as a mechanical support to the thinned imager. The butting gap is only 3 pixels (25μm) wide by design.
• A 5.4mW 0.0035mm2 0.48psrms-Jitter 0.8-to-5GHz Non-PLL/DLL All-Digital Phase Generator/Rotator in 45nm SOI CMOS.  K-H. Kim, et al. (IBM)  
  A non-PLL/DLL all-digital phase generator/rotator is realized in 45nm SOI CMOS. The circuit accepts 2 input phases plus interpolator controls and produces 4 output phases; it also supports relative I/Q adjustment for CDR applications. The 0.0035mm² circuit operates with phase error within 5° over a 0.8-to-5GHz range. At 5GHz, jitter is 0.48ps_rms, and the chip consumes 5.4mW from a 0.9V supply excluding the I/O buffers.
• An Array of 4 Complementary LC-VCOs with 51.4% W-Band Coverage in 32nm SOI CMOS.  D. Kim, et al. (IBM, Qualcomm)
  In order to provide wide range of oscillation frequencies in 100GHz band, an array of four switchable LC-VCOs, implemented in 32nm SOI CMOS. The VCOs cover 51.4% of W-band, occupy 40x35μm² and are scalable for an array implementation in nanometer SoC.
• A sub-1V Bandgap Voltage Reference in 32nm FinFET Technology.  A-J. Annema, et al. (U. Twente, NXP)
  A sub-1V bandgap reference circuit is implemented in 32nm SOI FinFET technology, introducing an architecture that minimizes the total required resistor value. The circuit operates correctly for supply voltages above 0.9V with a supply current of 14μA at room temperature. This design is interesting both because of the use of a lubistor as the bandgap diode element as well as a unique way the PTAT and CTAT voltages are combined via matched OTAs.
• A 460W Class-D Output Stage with Adaptive Gate Drive.  M. Berkhout (NXP)
  A compact 460W audio amplifier with low EMI is integrated on SOI CMOS. The Class-D output stage operating from an 85V supply is realized in an SOI-based BCD process. The output stage uses an adaptive gate driver that adjusts the speed of charging and discharging of the gates of the power MOSFETs depending on their terminal voltages. Measurements show smooth transitions at high output currents and output power is 460W at 10% THD.
• A 2ns-Read-Latency 4Mb Embedded Floating Body Memory Macro in 45nm SOI Technology.  A. P. Singh, et al. (Innovative Silicon, AMD)
  The paper describes a novel 4Mb DRAM memory macro using a floating-body SOI bitcell that is compatible with an SOI logic process. The macro features a single-ended capacitively coupled sense amplifier that results in 2ns read latency and a 4ns random cycle. The capacitorless memory cell achieves a macro density of 0.21mm² /Mb. The embedded memory macro is developed for high-performance microprocessors, using a single-transistor floating-body cell. Eight 4Mb macros are incorporated on a test-chip fabricated in a 45nm SOI logic process. Silicon measurements confirm 2ns read latency with a memory-macro operating window of 0.5V.

JOURNAL PAPERS

• Flexible photodetectors on plastic substrates by use of printing transferred single-crystal germanium membranes.  Hao-Chih Yuan, Jonghyun Shin, Guoxuan Qin, Lei Sun, Pallab Bhattacharya, Max G. Lagally, George K. Celler, and Zhenqiang Ma (U. Wisconsin-Madison, Soitec). Appl. Phys. Lett. 94, 013102 (January 6, 2009)
• Size and Thickness Effect on the Local Strain Relaxation in Patterned Strained Silicon-on-Insulator.  Diefeng Gu, Mingyao Zhu, George K. Celler, and Helmut Baumgart (Old Dominion U., College of William and Mary, Soitec).  Electrochemical and Solid-State Letters, 12 (4) H113-H116 (January 15, 2009)
• Monolithic integration of InP-based transistors on Si substrates using MBE.  W.K. Liu, D. Lubyshev, J.M. Fastenau, Y. Wua, M.T. Bulsara, E.A. Fitzgerald, M. Urteaga,
  W. Ha, J. Bergman, B. Brar, W.E. Hoke, J.R. LaRoche, K.J. Herrick, T.E. Kazior, D. Clark,
  D. Smith, R.F. Thompson, C. Drazek, N. Daval (IQE, MIT, Teledyne, Raytheon, Soitec) -  Journal of Crystal Growth, Vol. 311, Issue 7, pp. 1979-1983 (March 15, 2009)

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