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IEDM HIGHLIGHTS

 

Breakthroughs at
the IEDM

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). 

 

• Hitachi

Comprehensive Study on V_th Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation.  N. Sugii, et al. 

Silicon on Thin BOX (SOTB) for high-speed, low-power SOCs has the smallest V_th variation among all planar CMOS structures. Researchers have now found ways to reduce threshold voltage variation even further.

 

• Leti/ST/Soitec

High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding.  O. Weber, et al.

Undoped FD-SOI architectures are extremely effective in controlling V_t variability. Variation in the thickness of the top silicon is found not to be a significant factor in V_t variation; rather, thinning the top silicon minimizes V_t fluctuations. 

 

• IBM/Freescale/AMD

22nm Technology Compatible Fully Functional 0.1µm² 6T-SRAM Cell.  B. S. Haran, et al. 

Researchers from the IBM Alliance describe the world’s smallest fully functional SRAM memory cell. This work suggests that SRAM technology can be extended on planar SOI.

 

• Toshiba

Autonomous Refresh of Floating Body Cell (FBC).  T. Ohsawa, et al.

The physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without a sense amplifier operation. Therefore, FBC can be used to realize static RAM without periodical refresh while retaining data.

 

• NXP/TSMC/IMEC

First Observation Of Finfet Specific Mismatch Behavior And Optimization Guidelines For SRAM Scaling.  T. Merelle, et al.

V_t-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. This study provides guidelines for SRAM design in a FinFET technology.

 

• STMicroelectronics

190V N-Channel Lateral IGBT Integration in SOI 0.35µm BCD Technology.  M. Sambi, et al.

The integration of 190V N-Ch. LIGBT in SOI 0.35μm shrunk BCD technology is described. The novel device shows a very high saturation current and good HTRB robustness.

 

• AMD/U.Dresden

Implementation and Optimization of Asymmetric Transistors in Advanced SOI CMOS Technologies for High Performance Microprocessors.  J. Hoentschel, et al.

Sub-40nm L_gate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65nm and 45nm PD-SOI CMOS technologies. Product-level implementation shows a speed benefit of 12%.

 

• U.Tokyo

Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature.  J. Chen, et al.

Accurate electron mobility in nanowires on (110) SOI has been achieved by the split C-V method for the first time.

 

• Intel/Numonyx

Silicon Photonic Modulator and Integration for High-speed Applications (Invited).  L. Liao, et al.

Researchers presented recent results of a silicon photonic integrated chip that is capable of transmitting data at an aggregate rate of 200Gb/s. This is a continuation of the SOI-based work that Ansheng Liu of Intel wrote about in ASN#8.

 

 

Less Than Ever

By Dr. Nobuyuki Sugii,
Nano-process Research Department,
Hitachi Ltd

 

Hitachi demonstrates why it has the smallest V_th variability, and identifies the remaining components of random doping fluctuation.

In a “Comprehensive Study on V_th Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research Laboratory demonstrated that the planar FDSOI devices fabricated on SOTB have the smallest V_th variability among planar CMOS due to low-dose channel and back bias control.

Fig. 1 Schematic cross-section of SOTB and its features.
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Fig. 2 Comparison of Pelgrom coefficient A_Vt for NMOS. Smaller A_Vt value suggests smaller variability at the same T_ox. Painted areas correspond to HP and LSTP bulk obtained from the B_Vt value in (2).

The SOTB device is suitable because:

• it has a simple step-type retrograde doping profile,
• it needs no Halo implant, which make RDF phenomena complex, and
• applying back bias can provide additional information by modulating the depletion layer in the substrate.

The local variation components of the SOTB devices are about half or one third of the typical bulk values. Moreover, with good short channel effect immunity, the SOTB devices structure has weak dependence on V_ds and ΔL_g, thus smaller variability can be achieved.

Regarding the global variation, the relationship between SOI thickness, ΔΤ_Si, and V_th was studied. The result suggests that decreasing the silicon thickness variation, σT_SOI, is required for low dose channel devices.

In SOTB, this requirement can be mitigated. By keeping σT_SOI at 1nm or less in order to eliminate dropout transistors, the SOTB can further reduce V_th variation (virtually A_Vt<1.0 is expected due to extremely small local variation) by applying V_sub on each chip, because the variation due to σT_SOI is most likely global.

Finally, the authors conclude that in order to achieve smaller σV_th after reducing RDF requires:

• strict control of SCE immunity,
• decreasing body-thickness variation less than 1nm in standard deviation σ, and
• adaptive-bias control to compensate for global variation, which is the advantage of SOTB.

 

Fig. 3 Doping densities and V_th for samples I-III.

 

 

Sources Discovered

By Olivier Faynot,
Advanced SOI Technologies Development,
CEA-Leti Minatec

 

Leti, Soitec and ST have discovered the sources of threshold voltage variation in undoped, ultrathin FD-SOI architectures.

 

Fig. 1   TEM picture of the transistor architecture studied..
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Fig. 2 This figure shows the σ_{Vt, DIBL} as a function of T_Si measured by ellipsometry. V_t fluctuations due to σL and the DIBL are minimized by thinning T_Si.

 

 At the most recent IEDM conference, researchers from Leti, Soitec and STMicroelectronics presented a paper entitled, “High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding” (O. Weber et al, IEDM 2008).

The paper highlights the following breakthroughs:

• Sources responsible for local and inter-die threshold voltage (V_t ) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time.
• Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local V_t variability.
• Prior to this paper, some in the industry had postulated that in the most advanced SOI transistors, variation in the thickness of the top silicon layer (T_Si ) contributed to Vt variation. As described in this paper, it is found that SOI thickness (T_Si ) variations have a negligible impact down to T_Si = 7nm.

• T_Si scaling is shown to limit both local and inter-die V_t variability induced by gate length fluctuations.
• The highest matching performance ever reported for 25nm gate length MOSFETs is achieved (AV_t=0.95mV.μm), demonstrating the effectiveness of the undoped, ultra-thin FDSOI architecture in terms of V_t variability control.

 

Fig. 3 This figure shows the σV_t for a new process. By minimizing the short channel effects, σV_t of short L can be aligned with σV_t of long channel FETs.

Fig. 4 This graph summarized the various factors responsible for the local V_t variability in undoped 8.5nm-T_Si FDSOI devices with a HfO₂/TiN gate stack.

 

 

THE BASICS

IEDM’08

Conquering the Challenge of Threshhold Voltage Variability

At the most basic level, a transistor is turned on if the gate voltage is higher than the threshold voltage. That makes reducing variability in threshold voltage (which can be abbreviated as either σV_th or σV_t) critical.

Further compounding the problem, σV_th tends to increase with scaling, thereby preventing the reduction of supply voltage and standby leakage current. This is a major – if not the major – challenge for leading-edge CMOS.

In scaled bulk CMOS, random doping fluctuation (RDF) is a major cause of increasing σV_th.

It is widely recognized that with fully-depleted (FD) SOI, double gate or FinFETs with low (doping) dose channel structures can eliminate RDF, thus reducing variability.

In these papers presented by Hitachi and Leti at the most recent IEDM conference, significant breakthroughs were presented in understanding and reducing σV_th in FD-SOI architectures.

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