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SPECIAL SUPPLEMENT: SOI Industry Consortium*

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Reports & Papers

Floating Body Effects: Just the Facts

For designers who’ve never worked in SOI, rumors surrounding the “floating body effect” might make SOI  seem like too much of a challenge. A paper freely available on the SOI Industry Consortium website entitled “De-myth-tifying” the SOI Floating Body Effect by Bob Ulicki and Herb Reiter puts an end to any lingering misconceptions.

• As the authors point out, myths that Floating Body Effects in PD-SOI devices will cause serious performance issues or catastrophic functional problems are based on a simple lack of understanding of what is happening to body voltages during both startup and operating modes. 
• Once the basics of charge variation are understood, designers will realize that all they have to do is a bit more timing analysis using existing STA procedures. The standard tools from the major EDA Tool vendors render the Floating Body Effect transparent to the designer.
• This paper is the first in a series of SOI topics showing why the reality of physics speaks for much broader deployment of SOI. Other papers will also examine why economics will push SOI cost benefits for scaling through 22nm and beyond.

 

SOI Design Fundamentals

Engineering services company and Consortium member Infotech Enterprises has contributed an excellent white paper entitled Silicon On Insulator (SOI) Implementation. Author Narayana Murty Kodeti takes the designer through SOI basics, covering design specificities and techniques, and concluding with an ASIC design strategy. The paper is now freely available on the consortium website.

 

The SOI Consortium-sponsored FinFET study made the cover of the November 2009 issue of SST magazine.

SST Cover Story:
FinFET – SOI vs. Bulk at 22nm

Consortium members IBM, IMEC, Soitec and Freescale teamed up on the recent Comparison Study of FinFETs: SOI vs. Bulk – Performance, Manufacturing Variability and Cost.

The study was the cover story of the November 2009 issue of SST magazine. 

It evaluated performance, process variability, and cost differences between FinFETs fabricated with junction isolation on bulk silicon wafers, and FinFETs fabricated on SOI wafers. The analysis shows that fabrication on bulk and SOI wafers is for all practical purposes equivalent in performance and cost. However, bulk-based FinFETs are much more challenging to manufacture due to increased process variability.

 

The Growing Implementation Guide

The ninth chapter of the ongoing Implementation Guide has been posted. Contributed by Professor Denis Flandre, who heads up the microelectronics lab at the Université Catholique de Louvain, Design of SOI VCO/PLL Demos covers circuit examples of  VCO, CCO, PLL, and DLL devices. It includes design suggestions, optimization tips, comparisons of PD and FD SOI and case studies.

 

News Flash:
FD-SOI & low power workshop after the IEDM conference

The SOI Industry Consortium, CEA-Leti and Soitec are organizing an evening workshop entitled FD-SOI Readiness at the Hilton Baltimore on Wednesday the 9th of December 2009. The workshop is by invitation, particularly targeting IC makers, foundries, TCAD companies and IP houses. Complementing the technical papers and short courses presented during the IEDM conference, the workshop will be devoted to SRAM scaling, design porting from bulk to FD-SOI, BSIM models, the results of porting an ARM core to SOI, and TCAD with an outlook towards the specificities for FD-SOI. It provides a comprehensive review of the current state of technology presented by renowned experts in the field, and includes plenty of time for discussion and exchanges.

See the Consortium website for details

 

IMEC hosts FD-SOI for low power workshop

There was an excellent turnout at an all-day workshop on FD SOI for low-power applications, co-sponsored by IMEC and the SOI Industry Consortium. Held at the IMEC campus in Leuven, Belgium this past October, “FD SOI architecture, technology platform for low power applications for 22nm and beyond” featured speakers from IMEC, IBM, Hitachi, Soitec, UC Berkeley, ISi, CEA-Leti, ARM, Cadence, Synopsys and the SOI Industry Consortium. 

It addressed the entire ecosystem that will be necessary to bring the FDSOI technology to industrial maturity and widespread adoption. The morning session looked at the technology options for FDSOI CMOS architecture,  while the afternoon was devoted to SRAM scaling, the porting of the ARM core to PDSOI and TCAD, as well as other considerations for FDSOI.

In addition to the excellent presentations, those who attended indicated they appreciated the ample time between sessions to discuss and network, as well as the post-workshop reception.

 

Horacio Mendez, Executive Director of the SOI Industry Consortium, gave the opening talk.
- Bob Ulicki gave a talk on “SOI Fundamentals” on behalf of the consortium.

Design clinic

The SOI Consortium recently sponsored another very successful SOI Design Clinic. Co-located with ARM’s October TechCon3 developer conference in San Jose, this clinic followed ARM’s announcement of achieving 40% power savings by porting the ARM 1176 core to SOI (see ARM’s article in this edition of ASN). The full day of talks included:

• SOI Fundamentals by Bob Ulicki, SOI Industry Consortium
• Designing Low Power Circuits on SOI by Olivier Thomas, CEA-Leti
• Designing High Performance Microprocessors on SOI by Nghia Phan, IBM
• Design Tools, Flows and Methodologies for SOI: Digital, Mixed-Signal SoC and RF by Jim McMahon, Trisha Kristof and Michael Jacobs, Cadence

SOI circuit techniques were particularly appreciated, and the follow-up question and answer sessions were animated and engaging. 

However, it was clear from some of the questions that the consortium needs to continue in its efforts to reach the general design community about the basic benefits of SOI.

The design clinics are excellent educational vehicles. As one attendee commented, «I will be telling my colleagues that they should not miss this next time it is given.» 

Those who attended received a password through which they can download the presentations from the consortium website. 

Watch the website for news of upcoming clinics. Or, if you would like to arrange a design clinic in your region or tailored for your company, please contact the consortium.

 

Green success

The SOI: Simply Greener campaign launched this past summer was great success, generating a high level of interest.

The press gave it extensive coverage, with follow-up articles and interviews, including two video interviews that are available on the consortium website.

This effort accomplished two important objectives. First, it drove home the message that SOI delivers lower power. Secondly, it was a timely, socially responsible message on behalf of our industry. This message continues to gained traction. The SOI: Simply Greener logo is freely available on the website. Members and supporters are encouraged to download it for continued use in their own presentations.

 

New Members

The SOI Industry Consortium is open to any company, organization or academic institution with an interest in SOI.

See the website for information on how to join: www.soiconsortium.org

Now joining the membership roster are: Mentor Graphics and Kanasawa Institute of Technology.

 

 

* Legal Note: The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.

 

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