#10 | SUMMER 2008
posted July 16, 2008
SOI in Action
SOI in Action
In & Around Our Industry
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A listing of key upcoming events across the industry
Relevant papers from journals and recent conferences (VLSI and more)
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DESIGN FEATURE
SOI Design for the Mainstream
The SOI-enabling tools and IP that designers have been waiting for have arrived. Here, some industry leaders outline what they have on tap.
2008: ARM Lays the SOI Foundation
By Remy Pottier,
Head of SOI Marketing and Business Development,
This fall, ARM will be rolling out key physical IP libraries, opening the door to broad SOI adoption.
As the leading processor IP company, ARM is collaborating with industry partners to facilitate the adoption of SOI CMOS technology. ARM’s optimized SOI Physical IP libraries target development of high-speed and low dynamicpower SoC designs in 45nm SOI.
Promising benchmarks
By combining the ARM libraries with the inherent advantages of the SOI CMOS technology, chip designers can obtain up to 30% speed improvement over their traditional bulk CMOS processes.
The benchmarks comparing bulk CMOS and SOI CMOS technology are also showing an average of 40% power reduction at the same speed. The power savings are enabled by the fact that when you design for a given speed, your synthesis tool will pick a smaller cell in SOI to perform the same speed as in bulk.
Case studies
One case study concluded that a 9-track standard cell library in SOI could perform as fast as a 12-track library in an equivalent bulk CMOS technology. In this case, the surface of each individual cell was reduced by 25%, and both the leakage and the dynamic power of the circuit were also reduced.
Note that after routing, the 25% of area reduction at the cell level doesn’t translate into 25% reduction of die size, but in most cases a die reduction of 5-15% should be achievable.
New horizons
ARM Physical IP Solution
There are two main barriers of SOI adoption today: foundry adoption and IP availability. ARM Physical IP SolutionThere are two main barriers of SOI adoption today: foundry adoption and IP availability. ARM is working with select partners from the company’s massive ecosystem to facilitate the deployment of SOI CMOS technology for a broad range of applications. Initial efforts focus on enabling SOI to become mainstream for ASICs and ASSPs and to reduce the barriers to adoption cited above.
Because SOI CMOS technology offers alternative speed, power and area optimization to bulk CMOS for SoC design, SOI technology has already been adopted for high-end CPUs, servers and gaming platforms.
The second wave of adoption is already underway in networking applications, with storage and digital consumer markets showing indications of adoption in the near future.
ARM-optimized Physical IP libraries are on track for release in the coming months.
For additional information, please contact remy.pottier@arm.com.
By Kevin Kranen,
Director of Strategic Alliances,
With SOI, the performance-power trade-off can be balanced without changing design methodology.
If you’re a chip designer, what would it mean if you could measurably increase performance while keeping the same power consumption? Or, if you could meaningfully lower power consumption while retaining the same performance level? And what if you could do either one without changing methodology?
You might be really surprised.
But a growing design and manufacturing ecosystem that fosters mainstream design using SOI has begun to offer design teams exactly these benefits. The added performance and power reduction of SOI vs. bulk silicon, once the province of a few skilled, near-custom design teams, is becoming accessible to anyone using a mainstream commercial digital design flow today.
What’s different?
You might wonder: doesn’t SOI have different physical characteristics from bulk silicon, thus requiring special capabilities in EDA tools and flows? The answer is yes and no. SOI’s differences do drive some additional needs in EDA tools that work at the process, transistor, and geometry level.
TCAD must understand SOI recipes, circuit simulation requires specialized SPICE models plus specialized extraction for SOI device parasitics, and foundries need to supply DRC rule decks that include SOI rules.
Same design flow
At the gate level, though, carefully constructed and validated physical IP can abstract away virtually all of the SOI differences, while letting the natural circuit-level speed and power advantages of SOI shine through.
Clever circuit design coerces SOI gates to behave almost the same as bulk silicon gates, albeit faster. Intelligent characterization reshapes the remaining vestiges of SOI variance like the “history effect” into standard process corner data that can be exploited throughout implementation and sign-off via the Synopsys’ Galaxy™ Design Platform, with only the most minimal changes in flow.
As the SOI ecosystem fills out with a complete catalog of well-designed and characterized SOI physical IP, design teams can embrace the advantages of SOI using their current, productive design flows and experience.
Synopsys and our partners are ready to help both mainstream and leading edge designers build and verify SOI-based chips.
SOI in Galaxy Flow © 2007 Synopsis, Inc.
By Michael White,
Calibre nmDRC Product Manager,
How tools from Mentor keep SOI transparent for design; flexible and robust for tapeout.
The Mentor Graphics Calibre® nm Platform is built to provide maximum flexibility for designers and tapeout managers employing multiple technologies in their overall IC portfolio.
Although SOI requires substantially different and somewhat more complex design rules compared to bulk CMOS, they can be coded in a straightforward manner using the Calibre user-friendly rule definition language and rule writer interface. Customers can simply augment their bulk CMOS rule decks by adding specific rules for SOI.
Equation-based DRC simplifies DFM and other sophisticated SOI checks. © Mentor Graphics Corporation
The same applies to LVS (layout versus schematic) checks and device and extraction models—variations for process types and CDs (critical dimensions) can all be easily defined in flexible Calibre rules. For example, SOI requires a different approach to parasitic capacitance modeling, and these are easily handled within Calibre xRC rule decks.
The benefit for process developers is that they see the same physical verification flow, the same tool look and feel, the same rule language, and the same use model whether they are working with SOI, bulk CMOS or any other technology.
For designers using the verification tools, the differences between CMOS and SOI are transparent, so there is no learning curve or flow disruption.
Designs that yield well
As we move into smaller geometries, the verification checks will become even more complex and more demanding in terms of accuracy.
We are seeing much bigger swings between designs that yield well and designs that yield poorly due to greater manufacturing sensitivity to specific feature shapes and patterns. To address these issues the Calibre platform is introducing new capabilities such as Equation-based DRC (design rule checking) and Advanced Device Parameters (ADP).
Equation-based DRC allows users to define rules as continuous 3-D functions that directly model the underlying physical effects.
For complex interactions common at small geometries, this is far more convenient and accurate than creating large tables of linear approximations involving many variables. ADP extends the flexibility and accuracy of device models to handle new interactions that occur as CD shrinks below 45nm, resulting in improved extraction accuracy.
By Tony Bonaccio,
Distinguished Engineer,
IBM Systems and Technology Group
SOI provides key advantages for analog designers. Here’s how and why.
Many technical studies have shown that SOI CMOS technology offers substantial digital circuit performance improvements over bulk CMOS at the same lithography node.
As more CMOS fabs transition to SOI to enable these gains, analog circuit designers are faced with the task of accommodating the unique characteristics of this technology and leveraging them wherever possible.
Eliminates latchup
Figure 1section of a typical analog SOI . Cross device
Among the most important aspects in which SOI differs from bulk are substrate noise isolation, body voltage control, self-heating, and PN junction diode characteristics (see Figure 1).
The buried oxide layer that insulates SOI devices from the bulk substrate acts as a capacitor dielectric and blocks DC signals from coupling between devices. The most obvious advantage of this is in eliminating the possibility of latchup.
This has the further benefit of eliminating the need for extensive substrate or well contacts, saving area. The degree to which the buried oxide blocks AC signals depends strongly on the substrate resistance and the frequency.
Figure 2. Cross-section of a multi-fingered SOI device
Body contact strategies
SOI technologies offer device structures that permit the body of the device to be biased rather than float. A well-thought out body contact strategy is critical to successful analog circuit design.
DC circuit blocks like current almost always benefit from a body contact structure. Circuits in which the signal waveform is not periodic may also benefit from body contacts. Circuits with periodic input signals may perform optimally without body contacts because the periodic signal adequately determines the body potentials.
Other considerations
SOI devices are thermally isolated from one another as well as electrically isolated. If there are significant power differentials between devices that are intended to be electrically matched, self-heating can induce significant mismatch.
PN junction diodes are fabricated differently in SOI technology than they are in bulk CMOS. Lateral P-I-N diodes have been successfully produced in volume with excellent ideality over several decades of current. Such devices can be used to implement bandgap reference cells and temperature sensors in SOI.
As SOI becomes more popular, analog circuits are required for phase-locked loops, high-speed serial I/O circuits, and data converters. By leveraging SOI’s superior substrate noise isolation, body voltage manipulation, and by handling self-heating issues, analog circuit designers will reap the same benefits from SOI as digital designers do.
