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	<title>Advanced Substrate News</title>
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	<link>http://www.advancedsubstratenews.com</link>
	<description>News and stories from our industry and the applications it enables</description>
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		<item>
		<title>Consortium Website &#8211; What&#8217;s New</title>
		<link>http://www.advancedsubstratenews.com/2012/05/consortium-website-whats-new/</link>
		<comments>http://www.advancedsubstratenews.com/2012/05/consortium-website-whats-new/#comments</comments>
		<pubDate>Wed, 02 May 2012 10:35:35 +0000</pubDate>
		<dc:creator>Advanced Substrate News</dc:creator>
				<category><![CDATA[ASN #19]]></category>
		<category><![CDATA[Special supplement: SOI Industry Consortium]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5683</guid>
		<description><![CDATA[Presentations At the SOI Consortium’s 6th FD-SOI workshop (held just after ISSCC), excellent talks were given by STMicroelectronics, IBM, ARM, Leti, Soitec, Accelicon and UC Berkeley. Most of the presentations are freely available for downloading from the SOI Consortium website. As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve ...]]></description>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>FD-SOI – A Look at Consortium Benchmarking Results</title>
		<link>http://www.advancedsubstratenews.com/2012/05/fd-soi-a-look-at-consortium-benchmarking-results/</link>
		<comments>http://www.advancedsubstratenews.com/2012/05/fd-soi-a-look-at-consortium-benchmarking-results/#comments</comments>
		<pubDate>Wed, 02 May 2012 08:30:07 +0000</pubDate>
		<dc:creator>Advanced Substrate News</dc:creator>
				<category><![CDATA[ASN #19]]></category>
		<category><![CDATA[Special supplement: SOI Industry Consortium]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5665</guid>
		<description><![CDATA[STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES, Soitec and other leading semiconductor companies in the SOI Consortium recently participated in a benchmarking study. Each tackling different aspects, they detailed the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. The joint research was performed by using an ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/05/fd-soi-a-look-at-consortium-benchmarking-results/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Leti: Adding Strain to FD-SOI for 20nm and Beyond</title>
		<link>http://www.advancedsubstratenews.com/2012/04/leti-adding-strain-to-fd-soi-for-20nm-and-beyond/</link>
		<comments>http://www.advancedsubstratenews.com/2012/04/leti-adding-strain-to-fd-soi-for-20nm-and-beyond/#comments</comments>
		<pubDate>Mon, 30 Apr 2012 08:30:19 +0000</pubDate>
		<dc:creator>Olivier FAYNOT  and Francois ANDRIEU</dc:creator>
				<category><![CDATA[Advanced Substrate Corners]]></category>
		<category><![CDATA[ASN #19]]></category>
		<category><![CDATA[CEA-Leti]]></category>
		<category><![CDATA[R&D/Labnews]]></category>
		<category><![CDATA[14nm]]></category>
		<category><![CDATA[20nm]]></category>
		<category><![CDATA[28nm]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[FD-SOI]]></category>
		<category><![CDATA[foundry]]></category>
		<category><![CDATA[high-perf]]></category>
		<category><![CDATA[highperf]]></category>
		<category><![CDATA[Leti]]></category>
		<category><![CDATA[low-power]]></category>
		<category><![CDATA[modelling]]></category>
		<category><![CDATA[R&D]]></category>
		<category><![CDATA[SOC]]></category>
		<category><![CDATA[sSOI]]></category>
		<category><![CDATA[strain]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5642</guid>
		<description><![CDATA[Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/04/leti-adding-strain-to-fd-soi-for-20nm-and-beyond/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond</title>
		<link>http://www.advancedsubstratenews.com/2012/04/st-white-paper-excerpts-planar-fully-depleted-silicon-technology-to-design-competitive-soc-at-28nm-and-beyond/</link>
		<comments>http://www.advancedsubstratenews.com/2012/04/st-white-paper-excerpts-planar-fully-depleted-silicon-technology-to-design-competitive-soc-at-28nm-and-beyond/#comments</comments>
		<pubDate>Tue, 24 Apr 2012 20:14:16 +0000</pubDate>
		<dc:creator>Philippe FLATRESSE, Giorgio CESANA,  and Xavier CAUCHY</dc:creator>
				<category><![CDATA[ASN #19]]></category>
		<category><![CDATA[Design & Manufacturing]]></category>
		<category><![CDATA[In & Around Our Industry]]></category>
		<category><![CDATA[Soitec]]></category>
		<category><![CDATA[STMicroelectronics]]></category>
		<category><![CDATA[14nm]]></category>
		<category><![CDATA[20nm]]></category>
		<category><![CDATA[28nm]]></category>
		<category><![CDATA[apps]]></category>
		<category><![CDATA[ARM]]></category>
		<category><![CDATA[Cadence]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[embedded]]></category>
		<category><![CDATA[FD-SOI]]></category>
		<category><![CDATA[FinFET]]></category>
		<category><![CDATA[foundry]]></category>
		<category><![CDATA[high-perf]]></category>
		<category><![CDATA[low-power]]></category>
		<category><![CDATA[Mentor]]></category>
		<category><![CDATA[mobile]]></category>
		<category><![CDATA[modelling]]></category>
		<category><![CDATA[SOC]]></category>
		<category><![CDATA[Synopsys]]></category>
		<category><![CDATA[VTH]]></category>
		<category><![CDATA[wafers]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5580</guid>
		<description><![CDATA[STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/04/st-white-paper-excerpts-planar-fully-depleted-silicon-technology-to-design-competitive-soc-at-28nm-and-beyond/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond</title>
		<link>http://www.advancedsubstratenews.com/2012/04/chenming-hu-soi-can-empower-new-transistors-to-10nm-and-beyond/</link>
		<comments>http://www.advancedsubstratenews.com/2012/04/chenming-hu-soi-can-empower-new-transistors-to-10nm-and-beyond/#comments</comments>
		<pubDate>Mon, 23 Apr 2012 08:30:41 +0000</pubDate>
		<dc:creator>Chenming HU</dc:creator>
				<category><![CDATA[Advanced Substrate Corners]]></category>
		<category><![CDATA[ASN #19]]></category>
		<category><![CDATA[Professor's Perspective]]></category>
		<category><![CDATA[UC Berkeley]]></category>
		<category><![CDATA[14nm]]></category>
		<category><![CDATA[20nm]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[FD-SOI]]></category>
		<category><![CDATA[FinFET]]></category>
		<category><![CDATA[high-perf]]></category>
		<category><![CDATA[low-power]]></category>
		<category><![CDATA[Soitec]]></category>
		<category><![CDATA[wafers]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5561</guid>
		<description><![CDATA[FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length. The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/04/chenming-hu-soi-can-empower-new-transistors-to-10nm-and-beyond/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET</title>
		<link>http://www.advancedsubstratenews.com/2012/04/soitec-wafer-roadmap-for-fully-depleted-planar-and-3dfinfet/</link>
		<comments>http://www.advancedsubstratenews.com/2012/04/soitec-wafer-roadmap-for-fully-depleted-planar-and-3dfinfet/#comments</comments>
		<pubDate>Fri, 20 Apr 2012 10:02:10 +0000</pubDate>
		<dc:creator>Steve LONGORIA</dc:creator>
				<category><![CDATA[ASN #19]]></category>
		<category><![CDATA[Design & Manufacturing]]></category>
		<category><![CDATA[In & Around Our Industry]]></category>
		<category><![CDATA[Soitec]]></category>
		<category><![CDATA[14nm]]></category>
		<category><![CDATA[20nm]]></category>
		<category><![CDATA[22nm]]></category>
		<category><![CDATA[3D]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[FD-SOI]]></category>
		<category><![CDATA[FinFET]]></category>
		<category><![CDATA[foundry]]></category>
		<category><![CDATA[SOI]]></category>
		<category><![CDATA[wafers]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5537</guid>
		<description><![CDATA[Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/04/soitec-wafer-roadmap-for-fully-depleted-planar-and-3dfinfet/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>Interview With ST-Ericsson&#8217;s Chief Chip Architect: SOCs on 28nm FD-SOI &#8211; When, Why and How</title>
		<link>http://www.advancedsubstratenews.com/2012/04/interview-with-st-ericssons-chief-chip-architect-socs-on-28nm-fd-soi-when-why-and-how/</link>
		<comments>http://www.advancedsubstratenews.com/2012/04/interview-with-st-ericssons-chief-chip-architect-socs-on-28nm-fd-soi-when-why-and-how/#comments</comments>
		<pubDate>Fri, 06 Apr 2012 10:28:45 +0000</pubDate>
		<dc:creator>Advanced Substrate News</dc:creator>
				<category><![CDATA[ASN #19]]></category>
		<category><![CDATA[End-User Apps]]></category>
		<category><![CDATA[SOI In Action]]></category>
		<category><![CDATA[20nm]]></category>
		<category><![CDATA[28nm]]></category>
		<category><![CDATA[ARM]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[embedded]]></category>
		<category><![CDATA[FD-SOI]]></category>
		<category><![CDATA[foundry]]></category>
		<category><![CDATA[high-perf]]></category>
		<category><![CDATA[low-power]]></category>
		<category><![CDATA[mobile]]></category>
		<category><![CDATA[SOC]]></category>
		<category><![CDATA[ST]]></category>
		<category><![CDATA[ST-Ericsson]]></category>
		<category><![CDATA[wireless]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5498</guid>
		<description><![CDATA[ST-Ericsson&#8217;s Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs. &#160; Advanced Substrate News (ASN): Can you give us a bit of background on the markets you&#8217;re addressing? Louis Tannyeres (LT): Founded in 2009, ST-Ericsson is an industry leader in design, development and creation of ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/04/interview-with-st-ericssons-chief-chip-architect-socs-on-28nm-fd-soi-when-why-and-how/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions</title>
		<link>http://www.advancedsubstratenews.com/2012/03/sitime-using-soi-technology-to-develop-high-performance-mems-timing-solutions/</link>
		<comments>http://www.advancedsubstratenews.com/2012/03/sitime-using-soi-technology-to-develop-high-performance-mems-timing-solutions/#comments</comments>
		<pubDate>Mon, 26 Mar 2012 09:56:06 +0000</pubDate>
		<dc:creator>Paul HAGELIN  and Piyush SEVALIA</dc:creator>
				<category><![CDATA[In & Around Our Industry]]></category>
		<category><![CDATA[MEMS]]></category>
		<category><![CDATA[SiTime]]></category>
		<category><![CDATA[analog]]></category>
		<category><![CDATA[apps]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[embedded]]></category>
		<category><![CDATA[low-power]]></category>
		<category><![CDATA[SOI-MEMS]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5477</guid>
		<description><![CDATA[A radical SOI-based approach puts  SiTime at the top of the fast-growing silicon-based timing market. SiTime, an analog semiconductor company, is revolutionizing the timing components industry with silicon MEMS timing solutions that replace legacy quartz products. SiTime offers oscillators (XO, SPXO), voltage-controlled oscillators (VCXO), temperature compensated oscillators (TCXO), and multi-PLL, multi-output clock generators. All these ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/03/sitime-using-soi-technology-to-develop-high-performance-mems-timing-solutions/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>ST-Ericsson&#8217;s Next-gen NovaThor: This Year, at 28nm, on FD-SOI Wafers from Soitec</title>
		<link>http://www.advancedsubstratenews.com/2012/03/st-ericssons-next-gen-novathor-this-year-at-28nm-on-fd-soi-wafers-from-soitec/</link>
		<comments>http://www.advancedsubstratenews.com/2012/03/st-ericssons-next-gen-novathor-this-year-at-28nm-on-fd-soi-wafers-from-soitec/#comments</comments>
		<pubDate>Tue, 13 Mar 2012 11:25:09 +0000</pubDate>
		<dc:creator>Adele HARS</dc:creator>
				<category><![CDATA[Editor's Blog]]></category>
		<category><![CDATA[apps]]></category>
		<category><![CDATA[embedded]]></category>
		<category><![CDATA[FD-SOI]]></category>
		<category><![CDATA[high-perf]]></category>
		<category><![CDATA[low-power]]></category>
		<category><![CDATA[mobile]]></category>
		<category><![CDATA[Soitec]]></category>
		<category><![CDATA[ST-Ericsson]]></category>
		<category><![CDATA[STMicroelectronics]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5463</guid>
		<description><![CDATA[Big and official FD-SOI news: Soitec has announced that the company is supplying the FD-SOI wafers for ST-Ericsson&#8217;s next-generation of NovaThor 8540 smartphone/tablet processors. Starting at the 28nm node, this marks the industry&#8217;s first industrialization of the new planar, fully-depleted technology on ultra-thin SOI wafers. Soitec has just issued an official press release, but ST-Ericsson ...]]></description>
		<wfw:commentRss>http://www.advancedsubstratenews.com/2012/03/st-ericssons-next-gen-novathor-this-year-at-28nm-on-fd-soi-wafers-from-soitec/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Important News Comes Out of Recent FD-SOI Workshop</title>
		<link>http://www.advancedsubstratenews.com/2012/03/important-news-comes-out-of-recent-fd-soi-workshop/</link>
		<comments>http://www.advancedsubstratenews.com/2012/03/important-news-comes-out-of-recent-fd-soi-workshop/#comments</comments>
		<pubDate>Fri, 09 Mar 2012 10:57:32 +0000</pubDate>
		<dc:creator>Adele HARS</dc:creator>
				<category><![CDATA[Editor's Blog]]></category>
		<category><![CDATA[20/22nm]]></category>
		<category><![CDATA[28nm]]></category>
		<category><![CDATA[Agilent]]></category>
		<category><![CDATA[apps]]></category>
		<category><![CDATA[ARM]]></category>
		<category><![CDATA[conference]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[embedded]]></category>
		<category><![CDATA[FD-SOI]]></category>
		<category><![CDATA[IBM]]></category>
		<category><![CDATA[Leti]]></category>
		<category><![CDATA[low-power]]></category>
		<category><![CDATA[performance]]></category>
		<category><![CDATA[power]]></category>
		<category><![CDATA[SOC]]></category>
		<category><![CDATA[SOI Consortium]]></category>
		<category><![CDATA[Soitec]]></category>
		<category><![CDATA[STMicroelectronics]]></category>
		<category><![CDATA[UC Berkeley]]></category>

		<guid isPermaLink="false">http://www.advancedsubstratenews.com/?p=5430</guid>
		<description><![CDATA[The SOI Consortium&#8217;s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product ...]]></description>
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		<slash:comments>0</slash:comments>
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