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Articles by Xavier CAUCHY

Xavier CAUCHY

Xavier CAUCHY has written 3 articles on Advanced Substrate News.

Xavier Cauchy is Digital Applications & Strategic Marketing Manager at Soitec. Prior, he held technical and management positions at ST Microelectronics and BT Labs in SOC development (14 years) and Telecom R&D. He holds an MSc from ISEN (France) and King's College, U. London.

Which wafers for energy-efficient, fully-depleted transistor technologies? Thumbnail

Which wafers for energy-efficient, fully-depleted transistor technologies?

Posted by (Soitec) on November 21, 2012
In ASN #20, Design & Manufacturing, In & Around Our Industry
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To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher […]

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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Using FD-SOI to Design Competitive Chips Thumbnail

Using FD-SOI to Design Competitive Chips

Posted by (Soitec) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
Tagged with ,

FD-SOI solves challenges without complicating design and manufacturing. Designing a successful consumer-type IC requires a balanced combination of: packing in more differentiating features, reaching good performance with low power, keeping final application costs competitive, and respecting time-to-market. Figure 1 illustrates how just a few key features intrinsic to FD-SOI translate into advantages that serve those […]

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