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Articles by Jean-Luc PELLOIE

Jean-Luc PELLOIE

Jean-Luc PELLOIE has written 5 articles on Advanced Substrate News.

Director of SOI Technology, Fellow, ARM

Bulk logic designs for mobile apps port directly to FD-SOI Thumbnail

Bulk logic designs for mobile apps port directly to FD-SOI

Posted by Jean-Luc PELLOIE (ARM) on November 4, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of …

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Right Timing Thumbnail

Right Timing

Posted by Jean-Luc PELLOIE (ARM) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models. SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each …

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Cost Impact of Switching From Bulk to SOI Thumbnail

Cost Impact of Switching From Bulk to SOI

Posted by Jean-Luc PELLOIE (Soisic) on April 6, 2006
In ASN #4, Design & Manufacturing, In & Around Our Industry
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Overall the cost of an SOI chip is not higher than bulk and may even be lower, depending on the application. Cost is an important factor when developing a chip and going to production. Users of bulk substrates may ask how they can manage the added cost of the SOI substrate if they were to …

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First ASIC design kit for 90nm SOI process Thumbnail

First ASIC design kit for 90nm SOI process

Posted by Jean-Luc PELLOIE (Soisic) on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
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Soisic solution enables any ASIC designer using industry-standard EDA tools to move transparently into SOI     Until now, any company doing SOI chips has been using their own internal tools and design flows: there was no standard SOI ASIC design kit available. This effectively shut out fabless companies and complicated things for those companies …

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How to Use SOI for Low-Power Applications Thumbnail

How to Use SOI for Low-Power Applications

Posted by Jean-Luc PELLOIE (Soisic) on April 18, 2005
In ASN #1, Design & Manufacturing, In & Around Our Industry
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SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already proven their performance advantage in CPU applications. When compared with bulk CMOS at same power-supply voltage (Vdd) and same leakage current, SOI delivers a higher speed thanks to: • the combination of a lower junction …

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