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Articles by Carlos MAZURE

Carlos MAZURE

Carlos MAZURE has written 5 articles on Advanced Substrate News.

CTO, Soitec

3D at the Wafer Level

Posted by Carlos MAZURE (Soitec) on July 16, 2008
In Advanced Substrate Corners, ASN #10, R&D/Labnews
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Soitec’s core technologies are building blocks for 3D integration. At the wafer level, molecular bonding techniques and Smart Cut technology add significant value to 3D integration. A good application for these building blocks is backside illuminated image sensors (BIS), which is probably the most mature 3D technology and close to mass production. For standard front …

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High-k and Metal Gates Pave the Way to Further Innovation Thumbnail

High-k and Metal Gates Pave the Way to Further Innovation

Posted by Carlos MAZURE (Soitec) on May 11, 2007
In Advanced Substrate Corners, ASN #7, R&D/Labnews
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Here’s why HK+MG+SOI promises to be a winning combination. Seen as a necessary innovation to assure the IC scaling path, high-k gate dielectrics combined with metal gates have been in development for more than a decade. Recent announcements by IC technology leaders highlight the transition from R&D to early manufacturing for high-k and metal gate …

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UT BOX SOI: Engineering for Future Low-Power Applications Thumbnail

UT BOX SOI: Engineering for Future Low-Power Applications

Posted by Carlos MAZURE (Soitec) on December 6, 2006
In Advanced Substrate Corners, ASN #6, R&D/Labnews
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Ultra-thin buried oxide may solve some key design challenges at 32nm. Leading-edge microprocessors built on SOI have maximized performance while respecting the power budget by decoupling the Si surface from the substrate with a 150nm-thick buried oxide (BOX). However, moving towards low-power, high- or mid-performance CMOS applications, an increased coupling between the top layer of …

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Strained Silicon on Insulator: the Wafer Solution for Low-Power and High-Performance Devices

Posted by Carlos MAZURE (Soitec) on April 6, 2006
In Advanced Substrate Corners, ASN #4, R&D/Labnews
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sSOI is on-track for high-volume manufacturing at the 45nm node. The end of conventional scaling is a topic that has generated discussion and controversy within the semiconductor community. The fact is that IC density increase through device geometry shrinking no longer results in an IC performance increase if the scaling is not coupled to the …

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Substrate strategies for high-performance and low-power applications at 45 nm

Posted by Carlos MAZURE (Soitec) on July 11, 2005
In Advanced Substrate Corners, ASN #2, R&D/Labnews
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Two distinct technical strategies for advanced substrates will mark the 45nm node. One will be focused on high performance, the other driven by system-on-chip (SOC) applications, including low power, portable RF applications. The high performance path will drive the most advanced substrates and material innovations. Engineered substrate solutions include ultra-thin (UT) SOI, mobility enhancing substrates …

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