ASN #20 – The Move to Fully-Depleted: Manufacturing, Economics, Design (ST, CMP, IBS, SEH, Soitec, IBM…)

ASN #20

SOI In Action

EXCLUSIVE ASN INTERVIEW: ST’s Jean-Marc Chery on FD-SOI Manufacturing
In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics about the manufacturing process and the expected results.

IBS Study Concludes FD-SOI Most Cost-Effective Technology Choice at 28nm and 20nm
In a recent study entitled Economic Impact of the Technology Choices at 28nm/20nm, International Business Strategies (IBS) has found that those companies choosing FD-SOI at 28nm and/or 20nm should benefit from substantial savings in cost-per-die (see figure).
By Handel JONES (IBS)

In & Around Our Industry

Wafer Leaders Extend Basis for Global SOI Supply
It's a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world's biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.
By Adele HARS

Go Ahead – Take 28nm FD-SOI Out for a Test Drive
CMP is offering multi-project wafer runs of ST's 28nm FD-SOI technology on Soitec wafers with Leti models. It's the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes.
By Adele HARS

Which wafers for energy-efficient, fully-depleted transistor technologies?
To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher transistor density, meaningful performance gains and low power consumption.
By Xavier CAUCHY (Soitec)

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value
FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, and can compromise power, performance, and manufacturability.
By Ed NOWAK (IBM)

Advanced Substrate Corners

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value
FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, and can compromise power, performance, and manufacturability.
By Ed NOWAK (IBM)

Special supplement: SOI Industry Consortium

The Transition to Fully Depleted
The SOI Industry Consortium is actively engaged in supporting the industry’s transition to fully-depleted (FD) technologies.
By Horacio MENDEZ (SOI Industry Consortium)