ASN #19 – FD-SOI Industrialization (ST, ST-Ericsson, Soitec, Leti, UC Berkeley)

SOI In Action

Interview With ST-Ericsson’s Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.

In & Around Our Industry

Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET
Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures.
By Steve LONGORIA (Soitec)

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond
STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights.
By Philippe FLATRESSE, Giorgio CESANA and Xavier CAUCHY (Soitec)

Advanced Substrate Corners

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond
FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length.
By Chenming HU (UC Berkeley)

Leti: Adding Strain to FD-SOI for 20nm and Beyond
Work at Leti shows that strain is an effective booster for high-performance at future nodes.
By Olivier FAYNOT and Francois ANDRIEU (CEA-Leti)

Special supplement: SOI Industry Consortium

FD-SOI – A Look at Consortium Benchmarking Results

Consortium Website – What’s New