ASN #10 – GSA Survey; Mainstream SOI Design; BSI/ST
Celebrating 10 Issues of ASN
The mainstream joins the leading edge.
This is the tenth edition of Advanced Substrate News. When we first launched three years ago, 90nm SOI was the leading edge for a handful of companies. Now the leading edge is open to the fabless community and zipping along at 45nm.
But 90nm is still making exciting SOI news: that’s where much of the mainstream is today. So with this edition, we can celebrate the broadening range of SOI.
Many thanks to everyone who’s helped make ASN an SOI industry must-read. And to all of you designing and supporting new applications in and around the fast-expanding SOI ecosystem, we look forward to celebrating your success in the next ten issues, and beyond.
SOI In Action
3D ICs: Opportunities & Timing
A new study from Yole on 3D ICs sees a bright future for applications, markets and active layer transfer technology.
By Éric MOUNIER (Yole Développement)
In & Around Our Industry
Defect-Free High-Temperature Processing
Innovations in RTP play a key role in SOI wafer production for 45nm and beyond.
By Andreas TOENNIS (Mattson)
Victor Koldyaev Is Innovative Silicon’s First Fellow
Craig Factor named VP legal affairs and general counsel.
Tony Denayer New CEO at Cissoid
With a new CEO, new round of funding, and new product, customers and distribution, Cissoid is on a roll.
Analog Circuit Design in SOI
SOI provides key advantages for analog designers. Here’s how and why.
By Tony BONACCIO (IBM)
Calibre Adapts Easily to SOI
How tools from Mentor keep SOI transparent for design; flexible and robust for tapeout.
By Michael WHITE (Mentor Graphics)
Chip Designers: Having It All
With SOI, the performance-power trade-off can be balanced without changing design methodology.
By Kevin KRANEN (Synopsys)
2008: ARM Lays the SOI Foundation
This fall, ARM will be rolling out key physical IP libraries, opening the door to broad SOI adoption.
By Rémy POTTIER (ARM)
Advanced Substrate Corners
Smaller Pixels, Brighter Pictures
ST’s 3-megapixel back-illuminated image sensor for digital cameras leverages SOI, direct wafer-level bonding and thinning technologies, improving 1.45 x 1.45 µm² pixel quantum efficiency over 60%.
By François ROY (STMicroelectronics)
Industry’s First InP-based HBT on Silicon
Advanced engineered substrates are a key to the Raytheon-led DARPA COSMOS project to integrate compound semiconductors and silicon CMOS on a single chip.
By Thomas KAZIOR (Raytheon RF Components)
3D at the Wafer Level
Soitec’s core technologies are building blocks for 3D integration.
By Carlos MAZURE (Soitec)
Special supplement: SOI Industry Consortium
Consortium participation in member events and related industry conferences is a terrific way to get the word out.
The website is an excellent resource for both Consortium members and those interested in finding out more about SOI.
Getting the Word Out
The consortium’s director reports on recent events, activities and accomplishments.
By Horacio MENDEZ (SOI Industry Consortium)