ASN
Latest posts
Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers Thumbnail

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Posted by on June 12, 2013
In Advanced Substrate Corners, Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , , ,

Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions. Here’s a …

Continue ReadingView Comments (1)
Fully-Depleted SOI Workshop Follows VLSI in Kyoto Thumbnail

Fully-Depleted SOI Workshop Follows VLSI in Kyoto

Posted by on June 6, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , , , ,

The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto. The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium …

Continue ReadingLeave a Comment
Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing Thumbnail

Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing

Posted by (Peregrine Semiconductor) on May 27, 2013
In Design & Manufacturing, In & Around Our Industry, SOI In Action
Tagged with , , , , , , , , , ,

For more than 20 years, Silicon-on-Sapphire (SOS) technology—an advanced form of Silicon-on-Insulator (SOI) processing—has been used in semiconductor manufacturing. Recently, SOS in the form of UltraCMOS® technology has been designed into high-volume applications that have made it the technology of choice for several demanding RF applications. This technology combines a highly resistive substrate with CMOS …

Continue ReadingLeave a Comment
More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP Thumbnail

More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP

Posted by on May 22, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , ,

At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor. Here are some of the highlights (the complete presentations are all available from the CMP website). FD-SOI: …

Continue ReadingLeave a Comment
IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers Thumbnail

IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers

Posted by (ARM) on May 17, 2013
In Advanced Substrate Corners, Conferences
Tagged with , , , , ,

IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference Hyatt Regency Monterey Hotel and Spa, Monterey, California October 7th thru 10th, 2013 In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS …

Continue ReadingLeave a Comment