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Editor's Blog

FD-SOI/Shanghai Forum – Panel Sees Great Things Coming

Posted by on October 26, 2016
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shanghaifdsoi2016

Shanghai FD-SOI Forum Panel Discussion (left to right): Wayne Dai, CEO Verisilicon (moderator); Marshal Cheng, SVP Leadcore; Mahesh Tirupattur, EVP Analog Bits; Subramani Kengeri, VP GlobalFoundries; Handel Jones, CEO IBS; Christophe Maleville, VP Soitec. (Photo courtesy SOI Consortium and Verisilicon)

The panel discussion rounding out the day at the recent FD-SOI Forum in Shanghai ended an exciting week (GF’s 12nm FD-SOI & ecosys, Sony’s FD-SOI GPS in the Huami watch) on a decidedly optimistic note. Here’s a quick rundown of some of what was said.

(As soon as the presentations given earlier in the day are posted, we’ll take a quick cruise through those, too.)

Anything IOT is better on FD-SOI

Mahesh Tirupattur, EVP at low-power SERDES pioneer Analog Bits started it off with the reminder that for anything “always on” in IoT, FD-SOI’s always better. They had a terrific experience porting their SERDES IP to 28nm FD-SOI (which they detailed last spring – see the ppt here). The port from 28 bulk took 2 1/2 months (vs. to FinFET, which took almost 6). Even without using body bias, they got performance up by around 15% and leakage down by about 30% (he added that with body bias, they could get five times that).

He compared porting to FD-SOI to playing high school ball, vs. a port to FinFET which is like competing in the Olympics. ESD was different, but not a big deal – you just need to “read the manual”. Heating? Nothing an engineer can’t resolve. For IoT, FinFETs are like using a cannon to shoot a mosquito, he quipped.

He later ticked off a few more advantages of FD-SOI for the IoT design community: system cost, lower power – and here’s a particularly interesting observation – cheaper packaging. They were able to do wire bonding, so they were able to package a wearable video app in a plastic capsule. All things considered, FD-SOI offers the perfect solution, he said (and now he’s got silicon with “dramatic results” to prove it), adding that the IP guys need to evangelize this.

Moving really fast

GloFo VP Subramani Kengeri took a moment to look back before he looked forward. “FD-SOI is not new,” he reminded us. It was explored and researched for a decade. But at the beginning, CPUs were driving the industry, and everyone else followed suite. But now in mobile and IoT, RF is becoming more important, and what was good for the CPU is no longer what’s good for everything else. He tipped his hat to Soitec, ST and Leti, who “kept the lights on” and kept driving FD-SOI forward. Now with 5G on the horizon, FD-SOI is the enabler, he added.

He also noted that FD-SOI gets you the maximum memory onchip, and that with 12FDX, we’ll be seeing the world’s smallest SRAM. So that opens a new degree of freedom. The EDA partners have been working on automating body bias in the PDK for greater power management. He cites an ARM core with on-demand performance that can be used “intelligently”. Is it complicated? Not really, he says, especially if it’s automated. In fact he sees body bias opening the market for “extraordinary, innovative products” very soon. Key IP is in place. And it’s not just for IoT: aside from high-end CPUs, FD-SOI is optimal for everything. “Everything’s happening now, and it’s moving really fast,” he said.

Clear substrate path to 7nm

SOI wafer leader Soitec VP Christophe Maleville was asked if he saw any limit on manufacturing the ultra-thin wafers for the 7nm node. No problem, he said – they can do those wafers with 4nm of strained top silicon and a 10nm layer of insulating BOX. They’ve been working on FD-SOI wafers for over a decade, he reminded us, with Leti, IBM and ST. Back in 2013 when ST announced the Nova-Thor hitting 3GHz (or 1GHz at just 0.6V), everything was in place: the metrology was ready, reliability was controlled.

Today they’ve got a 15nm BOX layer in manufacturing, with no limits in moving to 10nm for customers going for very low power. For the strained top silicon needed for the 7nm node, they spent years working on strain with IBM et al in Albany, so they’re not starting from scratch. That substrate will be mature in just two years, so from a substrate point of view, he said, “7nm is no problem”.

Coming fast: lots of products (and a fab for China?)

In response to a follow-up question from a well-known analyst in the China tech industry, panel moderator and Verisilicon CEO Wayne Dai said that the design community in China has the skills to do FD-SOI, no problem. He’d like to see more IP, but FD-SOI has powerful advantages in terms of cost, analog/memory and back biasing.

Dai then asked the panelists if they thought we’d be seeing a foundry in China opting for FD-SOI by next year – all but one said yes. One thing all the panelists agreed on, however: they all expect to see FD-SOI products (and lots of them) on the stage at the Shanghai FD-SOI forum in 2017.