Tagged with design, foundries, IoT, modeling, RF SOI
Coupling Wave Solutions (CWS) has a new productivity tool called SiPEX, which enables RF-SOI designers to increase the number of design iterations—including Spice simulation—up to 10 times in the same time frame.
“With SiPEX, RF switch designers will be able to make their design changes in less than 15 minutes and obtain a few decibels (dB) of variation over silicon measurements in simulation. This is a dramatic improvement over current productivity levels,” said Brieuc Turluche, CEO of CWS.
“State-of-the-art RF front-end components require advanced design methodologies and tools. SiPEX helped us improve our productivity and close the gap between simulation and silicon measurements when optimizing the linearity of our chips,” said Greg Caltabiano, CEO of ACCO, a fabless semiconductor company developing innovative highly integrated semiconductor solutions for IoT and smart phone RF Front Ends.
With SiPEX, RF designers can either evaluate more design implementations in any given time frame, or accelerate the tape out to the RF-SOI foundry, shortening the time-to-market. SiPEX provides field solver-like accuracy. In addition, an RF-SOI foundry can back-annotate the silicon measurements in their PDK and ensure that Spice simulation with SiPEX will match the actual silicon measurements.
SiPEX is available as a plug-in for generic interconnect parasitic extraction tools including Mentor Graphic’s Calibre®.