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Editor's Blog

Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI (With More Details on What Designers Need to Know)

Posted by on June 8, 2014
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Following the big FD-SOI/EDA news, Synopsys has provided ASN with more details for designers.

Samsung_ST_logos             snps_logo

The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI (see press release here).

They’ve covered all the bases, so that designers going to Samsung’s foundry services for ST’s 28nm FD-SOI can hit the ground running. Samsung’s vice president of foundry marketing, Dr. Shawn Han, says, “28-nm FD-SOI is an ideal solution for customers looking for extra performance and power efficiency at the 28-nm node without having to migrate to 20-nm. Our close collaboration with Synopsys and ST will enable designers to reduce risk, accelerate time-to-market, minimize power and maximize performance to expand 28-nm FD-SOI adoption.”

Synopsys has collaborated closely with ST on FD-SOI for several years now – Galaxy is already successfully silicon-proven in several 28nm FD-SOI SoCs with multi-core processors, says the company. And just a few weeks ago, Synopsys announced that ST had standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization (see that press release here).

Synopsys says that the Galaxy Design Platform enables designers to take full advantage of FD-SOI’s low power and high performance. “Because the Galaxy Design Platform is silicon-proven on ST’s 28-nm FD-SOI process with multiple tapeouts of low power designs running in the gigahertz frequency range, customers can adopt this technology with confidence,” said Antun Domic, executive vice president and general manager, Design Group at Synopsys. “Combined with the Lynx Design System and DesignWare® IP, the Galaxy Design Platform enables engineers to derive maximum benefit from the FD-SOI process and our continued collaboration with ST and Samsung will ensure ease of adoption of FD-SOI for SoC design.”

The Galaxy Design Platform is a suite of design tools that work in an integrated way for design on both the digital and analog sides. It enables concurrent area, power and timing optimizations to enable engineers to optimize their designs for the ST 28nm FD-SOI process. Synopsys says the advanced design enablement features like the IC Compiler™ tool’s concurrent clock and data optimization, layer-aware optimization, physical datapath and comprehensive support for hierarchical and low-power design features can also be directly accessed by Lynx users for high-performance and low-power CPU and GPU design.

The Lynx Design System is an automation environment for chip designers. Lynx incorporates the full Galaxy Platform for both digital and analog implementation and for comprehensive design analysis. With technology portability and designer productivity as goals, the Galaxy flow in Lynx is architected technology independent. The accompanying technology plug-in structure enables design teams to quickly setup and implement on new technology nodes. Additionally, the automation architecture in Lynx enables the inclusion of third-party developed scripts and tools. Synopsys collaborates with the foundries to encapsulate technology-specific scripts and settings in the plug-in accelerating project setup and design time.

FD-SOI Specifics

Specifically for ST 28FDSOI, Synopsys collaborated with ST on the development of an ICC-Kit supporting UPF (Unified Power Format) and back-bias connections. Synopsys also implemented and validated a Lynx technology plug-in, integrating technology specific settings and scripts from the ICC-Kit into Lynx. The resulting combination significantly reduces designer overhead and implementation time for SOI nodes like ST 28FDSOI. Designers still need to add constraints and optimizations for their specific design, including the UPF files that specify the power intent. IC Compiler will connect the well ties and voltage converters in a manner consistent with the power-intent specified in the UPF Files (using scripts from the ICC-Kit).

All this should enable broader market adoption of ST’s 28nm FD-SOI technology for SoC design. “The close collaboration between ST design teams and Synopsys led to advanced silicon-proven design enablement solutions that fully leverage the performance and power promise of FD-SOI technology and provide the foundation needed to meet tight time to market windows,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics.

So there’s no need to wait. The Synopsys Galaxy Design Platform and Lynx Design System with support for ST and Samsung 28-nm FD-SOI process technology are available now from Synopsys. The 28-nm FD-SOI-enabled PDK, standard cells and memories for early design are available now from Samsung.

There’s no more doubt about it: for FD-SOI, it’s full speed ahead!

Note: Many thanks to Synopsys for help on the technical details in this piece.

ARM TechCon video/tutorial — recommended viewing:

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If you’re a designer looking for a good overview, there’s an excellent ARM TechCon 2013 video on FD-SOI posted on the Synopsys site. David Jacquet from ST shares the company’s FD-SOI approach to delivering optimized energy efficient solutions for the SoC market (he leads ST’s architecture activities for energy-efficient, high-performance CPU/GPU implementations). In his presentation (click on image above to view it) entitled, “Energy Efficient Implementation of ARM® Cortex©-A57/-A53 Processor Cores in FD-SOI Process Technology”, Jacquet begins with an overview of the FD-SOI process technology as an enabler for high-performance/low-power design. He then highlights the low-power implementation and verification methodology developed with Synopsys, including results and best practices.