Tagged with 14nm, design, FinFET, foundry, IBM, manufacturing, R&D, silicon-on-insulator, SOC, SOI, wafers
Authors: T. B. Hook, I. Ahsan, A. Kumar, K. McStay, E. Nowak, S. Saroop, C. Schiller, G. Starkey, IBM Semiconductor Research and Development Center
We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions. However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs. Accordingly, we use SOI as the base on which to build the FinFET, which not only simplifies the process but enables full realization of the potential of the device.
Fully depleted transistor technologies – both planar and SOI-based FinFET – offer excellent circuit operation for SRAM and DRAM due to the unsurpassed threshold voltage matching associated with the near-absence of doping. Additionally, good low voltage and stacked-fet circuit operation is realized due to the superior electrostatics associated with thin-body devices. Hardware data specifically illustrating these features is described below.
Threshold voltage matching and distribution
A significant improvement in threshold voltage mismatch has been well documented, as well as the degradation associated with adding doping to a FinFET. Less well publicized, however, is the even larger relative benefit to be found in thick-dielectric transistors, such as are used for analog and IO devices, and also in DRAM.
Random dopant fluctuation is not the only mechanism contributing to local threshold voltage mismatch, but it has historically been the largest contributor. It has been an even larger contributor for thicker dielectrics, as its baleful influence scales directly with dielectric thickness, unlike work function variations for example. Therefore an even more dramatic improvement in matching is found in thick-dielectric devices, as shown in Figure 1.
Figure 1. Mismatch data as a function of tinv for conventional doped (dotted line) and SOI FinFET (solid line). While the improvement in matching for ‘thin-oxide’ (1.2-1.5nm) is well known, less widely recognized is the even larger advantage obtained with ‘thick-oxide’ (>3nm) devices commonly used in IO and analog applications.
This improvement is important to IO and analog circuit operation and is vital to scaling the DRAM transfer device into the next generations.
In Figure 2 are shown probability plots of the threshold voltage for two DRAM transfer gate transistors and the profound improvement is obvious. The FinFET version actually has a considerably thicker gate dielectric than the conventional doped device and a shorter gate yet much better matching. The absence of thickness-driven matching opens up the device design space and enables optimization of the overall design, as well as allowing for the fundamental area scaling needed to move to the next generation.
Figure 2: Threshold voltage matching for DRAM transfer devices. Blue: 32nm generation thick oxide doping-controlled device. Red: 14nm generation thick oxide FinFET device. The FinFET device is shorter and has a thicker dielectric, yet the threshold voltage matching standard deviation is 0.7X that of the conventional planar doped version. This improvement is applicable also to other thick oxide devices, such as are used in IO and analog applications.
One of the most important benefits of improved matching is the much-desired reduction in the minimum operating voltage of the classic 6T SRAM. While the transistor matching data clearly show an advantage, putting it all together into a quantized FinFET SRAM cell with correct beta and gamma ratios and device centering to actually achieve low Vmin is a larger challenge.
Additionally, there may be other factors present in the scaled-up SRAM array that may not be so evident in the classic Pelgrom analysis from which most matching data are derived, such as some perturbation to line-edge-roughness, or nfet/pfet interactions, or any number of other possibilities.
Our data demonstrate that these concerns are surmountable and that real SOI FinFET SRAMs can operate at very low voltages. Figure 3 shows remarkable results on an SRAM array, with full read and write operation down to 400mV, without any assist circuitry. This is among the best results ever reported, even among those that utilize boost techniques and in-situ tuning of the devices.
Figure 3: Shmoo plot of 14nm SOI FinFET SRAM array showing a minimum operating voltage of 400mV, with full read and write capability. This result, as good or better than any yet reported, was obtained without benefit of the chip-specific tuning techniques associated with planar fully depleted devices or specialized independent double-gate FinFETs.
Low Voltage Circuit Operation
A considerable improvement in electrostatics associated with the FinFET over conventional doped devices not only enables the necessary gate-length scaling, but simultaneously improves the relative performance at reduced voltage and therefore reduces the power density at a given performance. While fully-depleted devices should in principle enjoy this advantage, the introduction of non-uniformity such as is involved with the tapered fin profile associated with bulk-based FinFET seriously compromises the output conductance and may obviate these expectations, as shown in Figure 4.
Figure 4: Representative bulk-based and SOI-based fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET.
The fin profile obtainable in SOI-based FinFETs is very nearly ideal and our data show that the low voltage benefits are fully realized in hardware. The frequencies of a suite of ring oscillator circuits (inverter, NANDs, and NORs) were measured on 14nm SOI-based FinFET hardware as a function of voltage and compared to the modeled expectations.
Figure 5 shows excellent correspondence with expectation, and also shows how the data are far superior to the voltage dependence of conventional planar technology.
Figure 5: Normalized frequency reduction as a function of Vdd for a suite of circuits (NANDs, NORs, and inverters). Near-perfect correspondence of the SOI FinFET data with the compact model is shown. This flatter voltage dependence is highly superior to that typical of doping-controlled planar technology.
Several key elements of the putative advantages of FinFETs over conventional devices have been demonstrated in hardware. By using SOI-based FinFET technology, the need for doping in the body has been effectively minimized, resulting in excellent matching characteristics in the undoped DRAM transfer device, and truly remarkable minimum operating voltage in the SRAM. Additionally, the superior voltage dependence and stacked-fet circuit behavior relative to conventional devices has also been demonstrated through measurements of ring oscillators of various sorts.