Adele HARS on July 3, 2013
Tagged with 14nm, 20nm, 28nm, cost, design, FD-SOI, FinFET, GlobalFoundries, IBM, manufacturing, silicon-on-insulator, SOI Consortium, Soitec, SSDOI, ST, strain, wafers
According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30% increase in performance over 28nm bulk LPS PolySiON, HPP increases die cost by 30%, while FD-SOI only increases die cost by 10%. (Both HPP and FD-SOI are HKMG/GateFirst).
Moving to 20nm, the graph indicates that FD-SOI gets an additional 25% performance increase: that’s terrific. This slide doesn’t give a performance increase figure for 20LPM, but it’s clearly way below 20nm FD-SOI.
Now there are no actual figures given for die cost at 20nm, but the position on the graph indicates that the shrink to 20nm on FD-SOI costs substantially less than the cost for shrinking on bulk. Later in the presentation, he indicated that a big part of the savings is in masks – FD-SOI requiring 10 fewer masks than bulk.
Interesting to note the position of 14XM, which is a bulk FinFET. Again, no actual figures are given, but die cost is substantially higher. However the relative performance increase does not appear to be very significant.
The presentation was made during the FD-SOI Workshop following VLSI in Kyoto, Japan. It is available from the SOI Consortium website.
Looking ahead to 14nm FD-SOI for high performance, ST’s Laurent Le Pailleur showed this interesting slide in his Kyoto Workshop presentation, 28nm FD-SOI Industrial Solution: Overview of Silicon Proven Key Benefits – again, lots of masks saved:
There are other presentations from the Workshop available on the Consortium website, including a terrific short course by David Jacquet of ST entitled Architectural choices & design-implementation methodologies for exploiting extended FD-SOI DVFS & body-bias capabilities.
For those wanting to know more about FinFETs on SOI, Terry Hook of IBM expanded on his excellent ASN article in a presentation entitled Elements for the Next Generation FinFET CMOS Technology. In particular, there are lots of clear explanations about why SOI makes a difference, and the role of wafer-level strain (aka “strained silicon directly on insulator” – which IBM calls SSDOI) wafers by Soitec.