Adele HARS on June 21, 2013
Tagged with 10nm, 14nm, 28nm, design, FD-SOI, FinFET, GlobalFoundries, Leti, manufacturing, Mentor, SEH, silicon-on-insulator, Soitec, ST, strain, wafers
STMicroelectronics CTO Jean-Marc Chery threw down the gauntlet when he told Electronics Weekly, “We must be ready with 14nm FD-SOI before anyone has FinFET at 14nm.”
Can they do it?
Yes, they can.
Unlike FinFETs, Planar FD-SOI is not a disruptive technology – FD-SOI is an extension of the planar CMOS we all know and love. Although the concept is over a decade old, the current technical development is moving at lightspeed.
When ST ported 28nm bulk to 28nm FD-SOI, they did it soup-to-nuts – including wafer processing – in under six months, with amazing results. At VLSI Kyoto, they reported that starting from a direct porting of a bulk planar CMOS SRAM design, the improvement in read current Iread was up to +50% (@Vdd=1.0V) and +200% (@ Vdd=0.6 V), respectively, compared with the original 28nm Low-Power (LP) CMOS technology.
The laying of the foundation – writing compact and SPICE models – has long been done. As Leti’s Olivier Rozeau explained in his article about Leti’s 28nm FD-SOI Compact models a few years ago in ASN, robust models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing.
SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to committing a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).
And when Mentor moved the Leti models to robust circuit simulators, they did it in under two years. Phenomenal! Leti’s 14nm models are now done, and the PDKs will be ready in Q3’13.
In fact, Leti is now working on models for 10nm FD-SOI, for which they’ll have PDKs in a year. That means all systems are go for 10nm FD-SOI in 2016. (And by the way, Leti CEO Laurent Malier also says that for boosting pFETs with SiGe, they’re seeing better results with FD-SOI than bulk FinFETs.)
What about manufacturing? Fabs typically take about a year to re-characterize their processes for a shrink. Moving from planar 28nm to 14nm FD-SOI is a straight shrink of what is essentially a legacy technology. Again, no showstoppers.
From a manufacturing standpoint, there are no gotchas, no special equipment. As Chery noted in an ASN interview last fall, “On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.”
The ultra-thin wafers have been ready for years, and have multiple sources including Soitec and SEH.
In terms of design, the design flows, methodologies and tools are the same as designers have always used. And, with FD-SOI, biasing efficiency (not possible in FinFETs) is an added bonus. ST has published figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at low power 0.6V – especially good news for anything with a battery.
In fact, Leti’s Malier recently highlighted that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
Leti’s finding that boosters like strain add another 10% to the performance figures: so overall with boosters they’re seeing +40% performance at the same supply voltage (Vdd) moving to 14nm, and another 30% moving to 10nm.
In discussing the two flavors of FD-SOI they have planned, Subi Kengeri, Vice President of Advanced Technology Architecture at GlobalFoundries points to this ST slide regarding timing:
The icing on the cake is the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In particular, the recently announced €360 million FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) is a plum. While the European workforce will certainly be the first to benefit from this, it is a strong endorsement of FD-SOI and really good news for the entire FD-SOI ecosystem.
Chery sees big opportunities for FD-SOI. At the ST Technodays (4 June 2013), he told ASN he’s targeting mobile, as well as networking/servers, gaming and apps, including set-top boxes. (And he also hinted that we should be on the look-out for some big announcements.)
So those folks that give bulk FinFETs an edge in the race to 14nm better keep the pedal to the metal and their eyes on the road as FD-SOI has a tuned engine and a smooth track. Buckle your seatbelts: the race is on.