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Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Posted by on June 12, 2013
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Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14).

By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions.

Here’s a quick preview.

Papers in the Jumbo-Joint Focus Sessions

JJ2-3: FDSOI Process/Design full solutions for Ultra Low Leakage, High Speed and Low Voltage SRAMs, R. Ranica et al., STMicroelectronics & CEA-LETI

In this paper from STMicroelectronics and CEA-LETI, six Transistor SRAM (6T- SRAM) cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage (0.197µm2) purposes are fabricated with 28 nm node FDSOI technology for the first time. Starting from a direct porting of bulk planar CMOS design, the improvement in read current Iread has been confirmed up to +50% (@Vdd=1.0V) & +200% (@ Vdd=0.6 V), respectively, compared with 28 nm Low-Power (LP) CMOS technology. Additionally, -100mV minimum operating voltage (Vmin) reduction has been demonstrated with 28 nm FDSOI technology. Alternative flip-well and single well architecture provides further speed and Vmin improvement, down to 0.42V on 1Mb 0.197µm2 . Ultimate stand-by leakage below 1pA on 0.120 µm2 bitcell at Vdd=0.6V is finally reached by taking the full benefits of the back bias capability of FDSOI.

Cross-sectional and plain view of FDSOI SRAM cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage(0.197µm2).

JJ1-8: First Demonstration of a Full 28nm High-k/Metal Gate Circuit Transfer from Bulk to UTBB FDSOI Technology Through Hybrid Integration, D. Golanski et al, ST Microelectronics and CEA-LETI

For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame of our hybrid technology. Competitive ESD performance for the same footprint is achieved through hybrid MOSFETS snap-back voltage reduction, obtained by implant engineering. In addition, we demonstrate that the performance of Silicon Controlled Rectifier (SCR) and ESD diodes are matched vs Bulk technology while maintaining the performance of FDSOI devices and without any additional masks.

JJ1-9: 2.6GHz Ultra-Wide Voltage Range Energy Efficient Dual A9 in 28nm UTBB FD-SOI, D. Jacquet et al. STMicroelectronics

This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to 1.2V, and forward body bias (FBB) techniques up to 1.3V bias voltage, thus enabling an extremely energy efficient implementation.
(Note: ST has indicated that 2.6GHz voltage range in the title dates from the time the paper was submitted earlier this year; the actual presentation will show a more extended range.)

JJ2-1 (Invited): Fully-Depleted Planar Technologies and Static RAM, T. Hook et al, IBM, STMicroelectronics, LETI

Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described.Thick- and thin-Bottom Oxide (BOX) variants are discussed.

JJ2-4: Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias, Y. Yamamoto et al, Low-power Electronics Association & Project (LEAP), The University of Tokyo

We demonstrated record 0.37 V minimum operation voltage (Vmin) of 2Mbit Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to small variability of SOTB (AVT~1.2-1.3 mVμm) and adaptive body biasing (ABB), Vmin was lowered down to ~0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
(Note: SOTB is a flavor of planar FD-SOI.)

In the Circuits Symposia

Paper T2-2: High Performance Si1-xGex Channel on Insulator Trigate PFETs Featuring an Implant- Free Process and Aggressively-Scaled Fin and Gate Dimensions, P. Hasemi et al., IBM & GlobalFoundries.

The adoption of advanced high-mobility Silicon Germanium (SiGe) channel materials with aggressively scaled Tri-gate pFETs on insulator is reported for the first time. SiGe is widely known as a suitable channel material for p-type MOS device, thanks to its higher hole mobility than that in conventional silicon material. In this paper, IBM and GlobalFoundries report a SiGe channel Tri-gate pFET with aggressively scaled Fin width (Wfin) and Gate length(Lg) dimensions, which is fabricated using SiGe on insulator substrate. Excellent electrostatic control down to Lg= 18 nm and Wfin< 18 nm has been reported. Using an optimized implant-free raised source/drain process, on-current Ion = 1.1 mA/µm at off-leakage current Ioff = 100 nA/µm and supply voltage Vdd= 1.0 V has been achieved.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm. (b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm.
(b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

15-4: A 28GHz Hybrid PLL in 32nm SOI CMOS, M. Ferriss et al, IBM

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is -110dBc/Hz at 10MHz offset. The 140μmx160μm 32μm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31mA from a 1V supply.

21-1: A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32 nm Digital SOI CMOS, L. Kull et al, IBM, EPFL

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time skew minimization and per-channel gain control based on low-power reference voltage buffers. Gain control of each sub-ADC is based on a fine-grain, robust R-3R ladder. The sub-ADC stacks the capacitive SAR DAC with the reference capacitor to reduce the area and enhance the settling speed. The speed and area optimized sub-ADC as well as a short tracking window of 1/8 period enable a low input capacitance and therefore render an input buffer unnecessary. The ADC achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2in 32nm CMOS SOI technology.

21-3: An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI, V.H.-C. Chen and L. Pileggi, Carnegie Mellon University

This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes 8.5mW with an FoM of 59.4fJ/conv-step.

In the Technology Symposia

5-3: Optimal Device Architecture and Hetero-Integration Scheme for III-V CMOS, Z. Yuan et al, Stanford University, Applied Materials, Sematech, Texas State University

Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional FinFETs. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

10-1: Benefits of Segmented Si/SiGe p-Channel MOSFETs for Analog/RF Applications, N. Xu et al, University of California, Applied Materials, Soitec

Segmented-channel Si and SiGe P-MOSFETs (SegFETs) are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics. SegFETs are found to have significant benefits due to their enhanced electrostatic integrity, lower series resistance and greater mobility enhancement, and hence show promise for future System-on-Chip applications.

14.5: 64nm Pitch Interconnects: Optimized for Designability, Manufacturability and Extendibility, C. Goldberg et al, STMicroelectronics, Samsung Electronics, GlobalFoundries, IBM

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell abutment conflicts. A Self-Aligned-Via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask. Yield ramp rate, groundrule validation, and reliability qualification were each accelerated by early brightfield adoption for trench and via, producing a robust cross-module process window. The resulting groundrules and process module have been plugged in to multiple technology nodes without re-development needed (e.g. 20LPM, 14nm FINFET, 14FDSOI, 10nm P&R levels). Scaling, performance, and reliability requirements are achieved across a spectrum of low power-high performance applications.

15-1: Innovative Through-Si 3D Lithography for Ultimate Self-Aligned Planar Double-Gate and Gate-All-Around Nanowire Transistors, R. Coquand et al, STMicroelectronics, CEA-LETI, IMEP-LAHC

This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2-Poly-Si gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances (ION of 1mA per μm at VT+0.7V) with excellent electrostatics (SS down to 62mV per dec and DIBL below 10mV per V at LG 80nm) are paving the way to the ultimate CMOS architecture. To meet all requirements of lowpower SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.

15-3: Scaling of Ω-Gate SOI Nanowire N- and P-FET Down to 10nm Gate Length: Size- and Orientation-Dependent Strain Effects, S. Barraud et al, CEA-LETI, CEA-INAC, STMicroelectronics, IMEP-LAHC

High-performance strained Silicon-On-Insulator nanowires with gate width and length scaled down to 10nm are presented. For the first time, effectiveness of sSOI substrates is demonstrated for ultra-scaled N-FET NW (LG=10nm) with an outstanding ION current and an excellent electrostatic immunity (DIBL=82mV/V). P-FET NW performance enhancement is achieved using in-situ etching and selective epitaxial growth of boron-doped SiGe for the formation of recessed Sources/ Drains (S/D). We show an ION improvement up to +100% induced by recessed SiGe S/D for LG=13nm P-FET NW. Finally, size- and orientation-dependent strain impact on short channel performances is discussed. <110> Si NWs provide the best opportunities for strain engineering.

17-2 (Late News): Experimental Analysis and Modeling of Self Heating Effect in Dielectric Isolated Planar and Fin Devices, S. Lee et al, IBM

Field Effect Transistors on SOI offer inherent capacitance and process advantages. The flow of heat generated at the drain junction may be impeded by dielectric isolation but an assessment must also account for conduction of heat through the gate stack and through the device contacts, and its impact on device characteristics should be captured by the scalable model to enable accurate circuit design. A quantitative comparison to 45nm planar SOI shows that while the scaled FinFET on dielectric devices show higher normalized thermal resistance, as expected from device scaling, the characteristic time constant for self heating is still well below the operating frequency of typical logic circuits, hence resulting in negligible self heating effect. For cases where the self heating becomes a factor, e.g., in high-speed I/O circuits, the same design methods can be applied for both planar and FinFET devices on dielectric isolation.