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IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI
Posted by Terence HOOK (IBM) on April 18, 2013Tagged with 14nm, design, FinFET, foundry, IBM, manufacturing, R&D, silicon-on-insulator, SOC, SOI, wafers
Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, reliability, and product performance.
Bulk vs. SOI basics
In bulk wafers, isolation is formed in a manner similar to planar devices, with implanted wells and shallow-trench-isolation oxide separating fins from one another.
With an SOI (silicon-on-insulator) wafer, however, the fins are formed in the silicon layer, the isolating dielectric is already extant, and no well implants are required.
Figure 1: Schematic representation of bulk junction and dielectric-isolated FinFETs
The most important differences in the devices formed in these two manifestations lie in the shape of the fin, the processes that determine the effective fin height, and the presence of doping, which consequently affects the device in many adverse ways such as the variability and the reliability.
The final realization of the full potential of fully-depleted FinFETs is dependent on optimally addressing the issues enumerated herein. Dielectric isolation is shown to provide superior characteristics in all of the above-named aspects. Figure 1 shows a schematic representation of FinFETs for the two isolation architectures, with the various critical points of distinction noted as are discussed below.
Fin Shape
Definition of the fins on an SOI wafer is relatively straightforward; vertical fin sidewalls may easily be obtained.
Figure 2: Typical bulk junction and dielectric-isolated FinFET fin profiles
In a bulk-based process, as the spaces between the lower, electrically inactive portions of the fins must be filled with an insulator, some angling of the fin is required to prevent the formation of voids.
Bulk and SOI fin profiles are pictured in Figure 2. As tapering the fin compromises the subthreshold slope and degrades the effective drive current as well as the output conductance, minimization of the taper is important to the electrical integrity of the device.
Bulk: Doping in the Fin
Whereas in an SOI design the transistor-transistor and subfin source-drain current paths are inherently interrupted by the dielectric layer, in a bulk-based process adequate doping for electrical isolation and latchup immunity needs to be established. This requires additional masking levels and connections for electrical bias.
Conventional design criteria of doping, depth, and overlay tolerances apply to the deep interdevice isolation wells, but suppression of undesired current in the drain-source region has unique features in the FinFET configuration.
Suppression of punchthrough current requires some level of doping at least in the bottom portion of the fin. The adverse effects of doping on mobility and random-dopant-fluctuation have been reported; non-uniform doping is particularly egregious as it increases capacitance without a concomitant increase in drive current.
However, the level of doping required depends on the alignment of the gate and the source junction depth. An optimum choice for the conjunction seeks to minimize the dopant required while respecting physical process window constraints (see Figure 3).
Figure 3: Short-channel effects as a function of doping and gate recess depth relative to the source junction depth in bulk FinFETs
Another adverse effect of doping in the fin is the implication for the gate work function. For junction-isolated FinFETs, the gate metal work function is established so as to provide the desired threshold voltage in the presence of doping; for undoped dielectric-isolated FinFETs the appropriate work function is closer to midgap, which reduces gate leakage and improves reliability.
Figure 4: Voltage operating range as a function of fin doping
Between RDF-driven Vmin and work function-driven Vmax, the operating window of bulk FinFETs is more limited than that of undoped SOI FinFETs (see Figure 4).
Product and Circuit Design Considerations
Designing with planar bulk technology has historically differed from planar SOI technology in three aspects: well contacts, self-heating, and floating body effects.
At the expense of area, planar bulk technology has enjoyed the advantages of controlling the threshold voltage through the well potential. No such benefit exists in bulk FinFET devices, as it is not possible to influence the transistor through the well bias except in the spurious and undesirable region below the active fin.
In fully-depleted devices the concept of a floating body (charge storage in an isolated neutral region) is not applicable, so SOI and bulk FinFETs behave the same way for all switching scenarios.
Self-heating effects, while not important for fast switching operation, can be relevant for DC circuits. While large-area planar structures will continue enjoy the advantage in thermal conduction relative to SOI traditionally observed, bulk and SOI FinFETs have very similar self-heating characteristics, as the only difference in thermal conductance is a tall, thin sliver of silicon, which provides only a small increase in thermal conductance.
While bulk FinFET technology has lower soft error rates than planar bulk technology, SOI FinFETs are better yet.
Variations
Fin height variation has a much more serious impact than the planar analog of transistor width variation. Wide transistors (i.e., many fins) have the same variation as narrow (i.e., few fins).
Figure 5: Calculated dependence of SOI and bulk transistors on key process variations, and relative variations in the two architectures
Whereas in the SOI-based version the electrical fin height is determined by the starting silicon thickness, in the bulk-based FinFET process the fin height is determined by several processes, and the distinction between “active” and “inactive” fin is blurred by the conjunction of the gate alignment with the source junction.
The sensitivities to various key variables have been calculated with hardware-calibrated 3D simulations, and the variation of those key parameters determined with respect to state-of-the-art processes (see Figure 5).
The fin variation-driven performance tolerance of a bulk FinFET is larger than that of an SOI FinFET. That benefit of SOI is not only found in sort yield and worst-case design corners, but smaller variation within a chip enables a faster chip for any given level of leakage.
Conclusion
Complete realization of the benefits of fully-depleted transistor architecture is affected by the choice of isolation. Increased range of operating voltage, process simplification, reduced variation, lower soft error rate, and higher circuit density are all features of a dielectric-isolated architecture.
For these reasons the ability of an SOI-based FinFET to reap the full benefits of fully depleted transistors is demonstrably superior to a doped, bulk-based implementation.
For bulk P-FinFET, people can recess the SiGe Source/Drain to introduce more strain, which is good for boosting hole mobilities. For SOI FinFET, you cannot even fully etch the Soure/Drain part of the fin, the induced channel strain will be very marginal.
Thank you for your comment on the fin recess and the strain, Our calculations concur that the removing the bulk fin to some level below
the local oxide and then refilling with silicon germanium can indeed increase the strain over the situation where the recess is restricted to
retain a lateral seed layer on the SOI. However, we calculate a maximum of 15% increase in stress with a deep recess, which translates to a meager 5% in pfet drive current, and an even more irrelevant 3% in AC performance. We must
keep in mind that the FinFET is tall and narrow, and what happens at the bottom doesn’t help the top very much. Even worse than the paltry benefit to performance, however, is the detrimental effect that such a deep junction has on the sub-fin punchthrough. Driving the junction deeper than absolutely necessary exacerbates that problem and requires even more doping to suppress.
SOI is too expensive…and bulk oxide induces several new problems intrinsic to oxide.
The accountants shiver when an electrons-and-holes guy such as myself has the temerity to comment on cost. Don’t anyone even imagine that I have been authorized to discuss pricing! Levity aside, I would like to say that no process costs “too much” if the alternative
does not work. Even at the dimensions appropriate for today’s technology, our calculations suggest that overall cost of the process is equivalent when you take into consideration the additional processing necessary for the fin formation and the isolation. Don’t
presume that proper isolation is just a couple of block masks and implants. If one then quantifies the cost in terms of yield loss from variability, and the cost in terms of lost performance from the non-optimum transistor design point, then paying more for the starting substrate starts to look like a bargain. Most importantly, focusing on today’s dimensions is not sufficient. Is the bulk wafer and junction isolation approach viable for future nodes? The industry needs a scalable solution, and the bulk approach is limited.
As for the other comment on “several new problems” I would be glad to attempt to ponder them if you could be more descriptive.
SOI substrates allowed for certain embedded memory options
, back biasing for multi Vt in SoC and
lower soft error rates for Planar generations
Do these carry over to finfets in addition to
Junction isolation and improved Electrostatics from vertical fin
profiles ?
FDSOI allows for interesting back bias options, but FinFETs, either on bulk or SOI substrates, are virtually insensitive to well bias. Only the very bottom of the fin is subject at all to the influence of the back bias.
Soft error rate for FinFETs on SOI substrates will be better than on bulk substrates, but it is only fair to point out that theFinFET architecture (the small junction area) provides for better SER than planar even for bulk substrates
I would like to make a suggestion — to make SOI better in the manufacturing. For yesrs, SOI has been claimed to be better in performance, among others. I think majority of pepole believe this claim.Still, they choose the bulk CMOS. The reason is simple. So far, whatever performance SOI is belived to be capable, the bulk CMOS can deliver consistently at a better manufacturing cost. In the end, users make their own pick.
The bulk CMOS is struggling, yes, but it still moving faster than most people have been expecting. It will be gone oone day and take the SOI with it, just like VHS has done to Beta. History always repeats.
I couldn’t agree more that the technically superior solution does not always prevail if there is a lesser, albeit adequate, less expensive solution available, or even a solution that has superior marketing and market penetration, such as VHS over Beta.
The real cost may or may not be reflected in the pricing; that is the province of someone other than me. What interests me is at what point the bulk solution is not longer just a poorer solution but is no longer viable at all. At the 10nm node? the 7nm node? Is it already mortally wounded at 14nm?
When further scaling fails to deliver benefits to the consumer at reasonable cost, indeed the landscape will change and some other focus will dominate the industry. While I say again that I am not the accountant here, the difference in cost between an SOI FinFET and a bulk FinFET (if indeed there really is any at all) is a small portion of the challenges facing scaling.
intresting study material for future research.
Hi,
Can u please give info on gate control in FINFET.
Thanks in advance .
Thank you for your interest.
With respect to ‘gate control’ it is unclear to me as to whether you are alluding to process-related control of the gate dimensions, or to the electrostatic control of the channel potential with the gate. I will attempt to say something about both items.
For Finfets, be they SOI or bulk, the electrostatic control is far superior to planar, be it PDSOI or bulk. Electrostatic control with FinFETs is also superior to planar FDSOI, but the discrepancy is not nearly so dramatic. Typical results are near-ideal subthreshold swing of 70mV/decade and DIBL of say, 50mV/V with FinFETs, as opposed to 100 mV/decade and 130mV/V for planar doping controlled devices. FDSOI results may be intermediate to this. Naturally, the details depend on the film thickesses and junction profiles and all of the details. We have found the bulk FinFET to be somewhat poorer in electrostatic control than the SOI FinFET, largely because of the generally poorer fin shape of the former, the top-bottom nonuniformity of conductance and the finite contribution of the subfin region (where the effective gate thickness is changing rapidly). Some discussion of this may be found in my presentation at http://www.soiconsortium.org/fully-depleted-soi/presentations/april-2013/.
As for process control of the physical gate, both versions of the 3D device rely primarily on the ‘sidewall’ of the gate to form the effective dimension of the gate length across most of its width, in contrast to the planar device. The fundamental difficulty lies in removing the unwanted dummy gate from the entire height of the fin while not eroding the top of the fin. The same issue obtains whether the underlying substrate is bulk or SOI. The channel length variation due to gate imaging, etch, and then replacement is expected to be much the same regardless of whether the device is built on bulk or SOI. Fin height variation is another story, of course. The electrical effective channel length depends also on the spacer width uniformity and the extension outdiffusion as well, where, as above, the non-zero contribution of the region beneath the active fin in the bulk manifestation would introduce variability, given that the key elements are all changing rapidly in that area.