Horacio MENDEZ (SOI Industry Consortium) on December 12, 2012
Tagged with Consortium, design, fabless, FD-SOI, FinFET, Fully Depleted, manufacturing
The SOI Industry Consortium is actively engaged in supporting the industry’s transition to fully-depleted (FD) technologies.
FD technologies offer:
- better electrostatics, so you’ve got stronger gate control;
- and lower channel doping, which enables better SRAMs that can operate stably at lower supply voltages – resulting in power savings of up to 40%.
There are two main flavors of FD technologies:
- planar (aka “2D” or FD-SOI), which leverage ultra-thin SOI wafers;
- vertical (aka “3D” or FinFET), which can be built on bulk or SOI wafers
Here are some of the main points we’re making.
FD Planar Closes the Gap
Planar FD transistors are cost effective and help close the FinFET gap while maintaining the design infrastructure.
- >30% advantage in performance in logic devices at 20nm (compared to planar bulk)
- 40% reduction in power
- over 50% reduction in power in memory (SRAM)
- cheaper/better isolation
- cheaper device integration
- improved SER
- better electrostatics
- better low voltage operation
- potential for back gate control
- improved Vmin
- no floating body issues
Planar FD significantly simplifies the manufacturing process, resulting in impressive per-die savings as compared to bulk – a point which is now garnering attention.
The value proposition is there: power, performance, cost and variability control. And perhaps most importantly, it’s available at 28nm to the fabless community now, through Consortium members STMicroelectronics and GlobalFoundries.
Fins on Oxide Are Superior
With oxide-isolated fins, the isolation process is simpler and less expensive. Many of the control issues are improved over bulk isolated FinFETs. The result is faster time-to-market and better power/performance.
With respect to variability control, starting on an SOI substrate enables:
- lower doping in Fins
- reduced (RDF) Variability
- lower Vmin; better analog
- superior Fin-height, Fin-width, taper, Control
In terms of process, starting on an SOI wafer as opposed to bulk means:
- no STI, no well implants
- reduced time-to-market
- greatly simplified fin etch, shape and control
- reduced fab cycle time
With SOI, dielectric isolation is superior. This results in:
- no sub-fin leakage path
- immunity from long-range parasitic conduction
- high-temperature operation integrity
- significantly better SER
- latch-up immunity
So when considering the bottom line, FinFET on insulator (compared to FinFET on bulk) is:
- 5 to 7 quarters faster
- less expensive
- better performance
- area savings
- supply current (Iddq) 30% lower
- minimum operating voltage (Vmin) 50mV lower
The Substrate Supply Chain is in place
There are at least 3 major substrate vendors supporting the transition to fully-depleted technologies. Their combined output will easily provide the required industry volume, and can be expanded if needed.
IDC predicts that worldwide smartphone shipments will reach over 1.16 billion in 2016. The processors will require about 1.3 million wafers/year. (See figure.) The combined capacity of the existing suppliers is 2.3-2.4 million wafers/year by early 2014. They have indicated that additional factory capacity can be put in place within a 12 month window, so incremental capacity can quickly reach 3 million wafers/year – more than enough to meet projected demand.
At the SOI Industry Consortium, we are extremely pleased with the traction we’re getting. With the first FD-SOI products hitting the shelves, we think 2013 will be an exciting year.